CD4034 Datasheet PDF - SYC


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CD4034
SYC

Part Number CD4034
Description CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register
Page 14 Pages

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CD4034
CMOS 8-Stage Static Bidirectional Parallel/Serial
Input/Output Bus Register
Features
Description
• High Voltage Types (20V Rating)
• Bidirectional Parallel Data Input
• Parallel or Serial Inputs/Parallel Outputs
• Asynchronous or Synchronous Parallel Data Loading
• Parallel Data-Input Enable on “A” Data Lines (3-State
Output)
• Data Recirculation for Register Expansion
• Multipackage Register Expansion
• Fully Static Operation DC-to-10MHz (typ.) at
VDD = 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Parallel Input/Parallel Output, Serial Input/Parallel Out-
put, Serial Input/Serial Output Register
• Shift Right/Shift Left Register
• Shift Right/Shift Left With Parallel Loading
• Address Register
• Buffer Register
• Bus System Register with Enable Parallel Lines at Bus
Side
• Double Bus Register System
• Up-Down Johnson or Ring Counter
• Pseudo-Random Code Generators
• Sample and Hold Register (Storage, Counting,
Display)
• Frequency and Phase Comparator
CD4034BMS is a static eight-stage parallel-or serial-input
parallel-output register. It can be used to:
1) bidirectionally transfer parallel information between two
buses, 2) convert serial data to parallel form and direct the
parallel data to either of two buses, 3) store (recirculate) par-
allel data, or 4) accept parallel data from either of two buses
and convert that data to serial form. Inputs that control the
operations include a single-phase CLOCK (CL), A DATA
ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S),
A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARAL-
LEL/SERIAL (P/S).
Data inputs include 16 bidirectional parallel data lines of
which the eight A data lines are inputs (3-state outputs) and
the B data lines are outputs (inputs) depending on the signal
level on the A/B input. In addition, an input for SERIAL DATA
is also provided.
All register stages are D-type master-slave flip-flops with
separate master and slave clock inputs generated internally
to allow synchronous or asynchronous data transfer from
master to slave. Isolation from external noise and the effects
of loading is provided by output buffering.
Pinout
CD4034BMS
TOP VIEW
81
72
63
54
45
36
27
18
“A” ENABLE 9
SERIAL INPUT 10
A/B 11
VSS 12
24 VDD
23 8
22 7
21 6
20 5
19 4
18 3
17 2
16 1
15 CLOCK
14 A/S
13 P/S
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CD4034BMS
Parallel Operation
Functional Diagram
A high P/S input signal allows data transfer into the register
via the parallel data lines synchronously with the positive
transition of the clock provided the A/S input is low. If the A/S
input is high the transfer is independent of the clock. The
direction of data flow is controlled by the A/B input. When
this signal is high the A data lines are inputs (and B data
lines are outputs); a low A/B signal reverses the direction of
data flow.
SI
AE
A/B
STEERING
LOGIC
A/S
P/S
CL
The AE input is an additional feature which allows many reg-
isters to feed data to a common bus. The A DATA lines are
enabled only when this signal is high.
Data storage through recirculation of data in each register
stage is accomplished by making the A/B signal high and the
AE signal low.
Serial Operation
SI
A1 Q
B1
SI
6
STAGES
A low P/S signal allows serial data to transfer into the regis-
ter synchronously with the positive transition of the clock.
The A/S input is internally disabled when the register is in
the serial mode (asynchronous serial operation is not
allowed).
Q
SI
A8 B8
The serial data appears as output data on either the B lines
(when A/B is high) or the A lines (when A/B is low and the
AE signal is high).
Register expansion can be accomplished by simply cascad-
ing CD4034BMS packages.
The CD4034BMS is supplied in these 24 lead outline pack-
ages:
Braze Seal DIP H4V
Ceramic Flatpack H4P
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Specifications CD4034BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 10 µA
2
+125oC
- 1000 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 10 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
Except A and B Lines
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
Except A and B Lines
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
0.53 - mA
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
1.4 - mA
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
1
+25oC
- -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.5 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
7
+25oC
VOH > VOL < V
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.5 V
(Note 2)
Input Voltage High
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5
-
V
(Note 2)
Input Voltage Low
VIL VDD = 15V, VOH > 13.5V,
1, 2, 3
+25oC, +125oC, -55oC -
4V
(Note 2)
VOL < 1.5V
Input Voltage High
VIH VDD = 15V, VOH > 13.5V,
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
(Note 2)
VOL < 1.5V
Tri-State Output
Leakage
IOZL VIN = VDD or GND VDD = 20V
VOUT = 0V
1
2
+25oC
+125oC
-0.4 - µA
-12 - µA
VDD = 18V
3
-55oC
-0.4 - µA
Tri-State Output
Leakage
IOZH VIN = VDD or GND VDD = 20V
VOUT = VDD
1
2
+25oC
+125oC
- 0.4 µA
- 12 µA
VDD = 18V
3
-55oC
- 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
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Specifications CD4034BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
Propagation Delay
TPHL VDD = 5V, VIN = VDD or GND
Parallel In to Parallel Out TPLH (Notes 1, 2)
Propagation Delay
3 State
AE to Out ‘A’
Propagation Delay
3-State AE to Out ‘A’
TPLZ VDD = 5V, VIN = VDD or GND
TPHZ (Notes 2, 3)
TPZL VDD = 5V, VIN = VDD or GND
TPZH (Notes 2, 3)
Transition Time
TTHL VDD = 5V, VIN = VDD or GND
TTLH (Notes 1, 2)
Maximum Clock Input
Frequency
FCL VDD = 5V, VIN = VDD or GND
(Note 2)
GROUP A
SUBGROUPS TEMPERATURE
9 +25oC
10, 11
+125oC, -55oC
9 +25oC
10, 11
+125oC, -55oC
9
10, 11
9
10, 11
9
10, 11
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
LIMITS
MIN MAX
- 700
- 945
- 400
- 540
- 400
- 540
- 200
- 270
2-
1.48 -
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
IDD VDD = 5V, VIN = VDD or GND
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL VDD = 5V, No Load
VOL VDD = 10V, No Load
VOH VDD = 5V, No Load
VOH VDD = 10V, No Load
IOL5 VDD = 5V, VOUT = 0.4V
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
NOTES
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
TEMPERATURE
-55oC, +25oC
+125oC
-55oC, +25oC
+125oC
-55oC, +25oC
+125oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+125oC
-55oC
+125oC
-55oC
+125oC
-55oC
+125oC
-55oC
+125oC
-55oC
+125oC
-55oC
LIMITS
MIN MAX
-5
- 150
- 10
- 300
- 10
- 600
- 50
- 50
4.95 -
9.95 -
0.36 -
0.64 -
0.9 -
1.6 -
2.4 -
4.2 -
- -0.36
- -0.64
- -1.15
- -2.0
- -0.9
- -1.6
UNITS
µA
µA
µA
µA
µA
µA
mV
mV
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
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