CAT25256 Datasheet PDF - ON Semiconductor

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CAT25256
ON Semiconductor

Part Number CAT25256
Description 256-Kb SPI Serial CMOS EEPROM
Page 19 Pages


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CAT25256
256-Kb SPI Serial CMOS
EEPROM
Description
The CAT25256 is a 256−Kb Serial CMOS EEPROM device
internally organized as 32Kx8 bits. This features a 64−byte page write
buffer and supports the Serial Peripheral Interface (SPI) protocol. The
device is enabled through a Chip Select (CS) input. In addition, the
required bus signals are clock input (SCK), data input (SI) and data
output (SO) lines. The HOLD input may be used to pause any serial
communication with the CAT25256 device. The device features
software and hardware write protection, including partial as well as
full array protection.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.*
Features
20 MHz (5 V) SPI Compatible
1.8 V to 5.5 V Supply Voltage Range
SPI Modes (0,0) & (1,1)
64−byte Page Write Buffer
Additional Identification Page with Permanent Write Protection
(New Product)
Self−timed Write Cycle
Hardware and Software Protection
Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
8−lead PDIP, SOIC, TSSOP and 8−pad UDFN Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
SI
CS
WP
HOLD
SCK
CAT25256
SO
VSS
Figure 1. Functional Symbol
* Available for New Product (Rev. E)
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SOIC−8
V SUFFIX
CASE 751BD
UDFN−8
HU4 SUFFIX
CASE 517AZ
SOIC−8
X SUFFIX
CASE 751BE
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATIONS
CS 1
SO
WP
VSS
VCC
HOLD
SCK
SI
PDIP (L), SOIC (V, X), TSSOP (Y),
UDFN (HU4)
(Top View)
** Not recommended for new designs.
PIN FUNCTION
Pin Name
Function
CS Chip Select
SO Serial Data Output
WP Write Protect
VSS Ground
SI Serial Data Input
SCK
Serial Clock
HOLD
Hold Transmission Input
VCC Power Supply
†The exposed pad for the UDFN package can be left
floating or connected to Ground.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 8
1
Publication Order Number:
CAT25256/D



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CAT25256
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Operating Temperature
Ratings
−45 to +130
Units
°C
Storage Temperature
−65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min Units
NEND (Note 3, 4) Endurance
1,000,000
Program / Erase Cycles
TDR Data Retention
100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
4. The new product revision (E) uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when
a single byte has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order
to benefit from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS − MATURE PRODUCT
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min Max
ICCR
Supply Current
(Read Mode)
Read, VCC = 5.5 V,
SO open
10 MHz / −40°C to 85°C
5 MHz / −40°C to 125°C
2
2
ICCW
Supply Current
(Write Mode)
Write, VCC = 5.5 V,
SO open
10 MHz / −40°C to 85°C
5 MHz / −40°C to 125°C
4
4
ISB1
ISB2
IL
ILO
VIL
VIH
VOL1
VOH1
VOL2
VOH2
Standby Current
Standby Current
Input Leakage Current
Output Leakage
Current
VIN = GND or VCC, CS = VCC,
WP = VCC, HOLD = VCC,
VCC = 5.5 V
VIN = GND or VCC, CS = VCC,
WP = GND, HOLD = GND,
VCC = 5.5 V
VIN = GND or VCC
CS = VCC,
VOUT = GND or VCC
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
VCC > 2.5 V, IOL = 3.0 mA
VCC > 2.5 V, IOH = −1.6 mA
VCC > 1.8 V, IOL = 150 mA
VCC > 1.8 V, IOH = −100 mA
TA = −40°C to +85°C
TA = −40°C to +125°C
TA = −40°C to +85°C
TA = −40°C to +125°C
TA = −40°C to +85°C
TA = −40°C to +125°C
−2
−1
−1
−0.5
0.7 VCC
VCC − 0.8 V
VCC − 0.2 V
1
3
4
5
2
1
2
0.3 VCC
VCC + 0.5
0.4
0.2
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
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CAT25256
Table 4. D.C. OPERATING CHARACTERISTICS − NEW PRODUCT (Rev E)
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min Max
ICCR
Supply Current
(Read Mode)
ICCW
Supply Current
(Write Mode)
Read, SO open /
−40°C to +85°C
Read, SO open /
−40°C to +125°C
Write, CS = VCC/
−40°C to +85°C
Write, CS = VCC/
−40°C to +125°C
VCC = 1.8 V, fSCK = 5 MHz
VCC = 2.5 V, fSCK =10 MHz
VCC = 5.5 V, fSCK = 20 MHz
2.5 V< VCC < 5.5 V,
fSCK = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 5.5 V
2.5 V< VCC < 5.5 V
0.8
1.2
3.0
2.0
1.5
2
2
2
ISB1
ISB2
IL
ILO
VIL1
VIH1
VIL2
VIH2
VOL1
VOH1
VOL2
VOH2
Standby Current
Standby Current
Input Leakage Current
Output Leakage
Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
VIN = GND or VCC,
CS = VCC, WP = VCC,
VCC = 5.5 V
TA = −40°C to +85°C
TA = −40°C to +125°C
VIN = GND or VCC,
CS = VCC, WP = GND,
VCC = 5.5 V
TA = −40°C to +85°C
TA = −40°C to +125°C
VIN = GND or VCC
CS = VCC
VOUT = GND or VCC
TA = −40°C to +85°C
TA = −40°C to +125°C
VCC 2.5 V
VCC 2.5 V
VCC < 2.5 V
VCC < 2.5 V
VCC 2.5 V, IOL = 3.0 mA
VCC 2.5 V, IOH = −1.6 mA
VCC < 2.5 V, IOL = 150 mA
VCC < 2.5 V, IOH = −100 mA
−2
−1
−1
−0.5
0.7 VCC
−0.5
0.75 VCC
VCC − 0.8 V
VCC − 0.2 V
1
3
3
5
2
1
2
0.3 VCC
VCC + 0.5
0.25 VCC
VCC + 0.5
0.4
0.2
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
Table 5. PIN CAPACITANCE (Note 5) (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V)
Symbol
Test
Conditions
Min Typ Max Units
COUT
Output Capacitance (SO)
VOUT = 0 V
8 pF
CIN Input Capacitance (CS, SCK, SI, WP, HOLD)
VIN = 0 V
8 pF
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
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CAT25256
Table 6. A.C. CHARACTERISTICS − MATURE PRODUCT
(TA = −40°C to +85°C (Industrial) and TA = −40°C to +125°C (Extended).) (Notes 6, 9)
VCC = 1.8 V − 5.5 V / −405C to +855C
VCC = 2.5 V − 5.5 V / −405C to +1255C
VCC = 2.5 V − 5.5 V
−405C to +855C
Symbol
Parameter
Min Max Min Max Units
fSCK
tSU
tH
Clock Frequency
Data Setup Time
Data Hold Time
DC 5 DC 10 MHz
40 20 ns
40 20 ns
tWH SCK High Time
75
40 ns
tWL SCK Low Time
75
40 ns
tLZ
tRI (Note 7)
tFI (Note 7)
HOLD to Output Low Z
Input Rise Time
Input Fall Time
50 25 ns
2 2 ms
2 2 ms
tHD HOLD Setup Time
0
0 ns
tCD HOLD Hold Time
10
10 ns
tV Output Valid from Clock Low
tHO Output Hold Time
tDIS Output Disable Time
0
75 40 ns
0 ns
50 20 ns
tHZ HOLD to Output High Z
100 25 ns
tCS CS High Time
140
70 ns
tCSS
tCSH
tCNS
CS Setup Time
CS Hold Time
CS Inactive Setup Time
30
30
20
15 ns
15 ns
15 ns
tCNH
CS Inactive Hold Time
20
15 ns
tWPS
WP Setup Time
10
tWPH
WP Hold Time
100
tWC (Note 8)
Write Cycle Time
5
6. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 50 pF
7. This parameter is tested initially and after a design or process change that affects the parameter.
10
60
ns
ns
5 ms
8. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
9. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). tCSH timing specification is valid
for die revision C and higher. The die revision C is identified by letter “C” or a dedicated marking code on top of the package. For
previous product revision (Rev. B) the tCSH is defined relative to the negative clock edge.
Table 7. POWER−UP TIMING (Notes 7, 10)
Symbol
Parameter
Max Units
tPUR
Power−up to Read Operation
1
tPUW
Power−up to Write Operation
1
10. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
ms
ms
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