CAT24C512 Datasheet PDF - ON Semiconductor

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CAT24C512
ON Semiconductor

Part Number CAT24C512
Description 512 kb I2C CMOS Serial EPROM
Page 17 Pages


CAT24C512 datasheet pdf
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CAT24C512
512 Kb I2C CMOS Serial
EEPROM
Description
The CAT24C512 is a 512 Kb Serial CMOS EEPROM, internally
organized as 65,536 words of 8 bits each.
It features a 128−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
External address pins make it possible to address up to eight
CAT24C512 devices on the same bus.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
Supports Standard, Fast and Fast−Plus I2C Protocol
1.8 V to 5.5 V Supply Voltage Range
128−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
8−pin PDIP, SOIC, TSSOP, MSOP, 8−pad UDFN and 8−ball WLCSP
Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
VCC
SCL
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TSSOP−8
Y SUFFIX
CASE 948AL
UDFN−8
HU5 SUFFIX
CASE 517BU
SOIC−8
W SUFFIX
CASE 751BD
SOIC−8
X SUFFIX
CASE 751BE
PDIP−8
MSOP−8
L SUFFIX
WLCSP−8*
Z SUFFIX
CASE 646AA C8A SUFFIX CASE 846AD
CASE 567JL
* Preliminary. Please contact factory.
PIN CONFIGURATIONS
A0
1
VCC
Pin A1
Reference
A1 WP
A2
SCL
SDA
VCC
VSS
SDA
SCL
PDIP (L), SOIC (W, X),
TSSOP (Y), MSOP (Z)
UDFN (HU5)
(Top View)
A2
VSS
A1
WP
A0
For the location of
Pin 1, please consult
the corresponding
package drawing.
WLCSP (C8A)
(Top View)
A2, A1, A0
WP
CAT24C512
SDA
VSS
Figure 1. Functional Symbol
Pin Name
A0, A1, A2
SDA
SCL
WP
VCC
VSS
PIN FUNCTION
Function
Device Address
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 7
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
1 Publication Order Number:
CAT24C512/D



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24512A
AYMXXX
G
SOIC−8 (W, X)
C9L
ALL
YM
G
UDFN−8 (HU5)
CAT24C512
MARKING DIAGRAMS
24512A = Specific Device Code
A = Assembly Location Code
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
G = Pb−Free Microdot
C9L = Specific Device Code
A = Assembly Location Code
LL = Last Two Digits of Assembly Lot Number
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
G = Pb−Free Microdot
24512A
AXXX
YYWWG
PDIP−8 (L)
C12A
AYMXXX
G
TSSOP−8 (Y)
C9YM
AXX
G
MSOP−8 (Z)
C9A
AYW
WLCSP (C8A)
24512A = Specific Device Code
A = Assembly Location Code
XXX = Last Three Digits of Assembly Lot Number
YY = Production Year (Last Two Digits)
WW = Production Week (Two Digit)
G = Pb−Free Designator
C12A
A
Y
M
XXX
G
= Specific Device Code
= Assembly Location Code
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Last Three Digits of Assembly Lot Number
= Pb−Free Microdot
C9 = Specific Device Code
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
A = Assembly Location Code
XX = Last Two Digits of Assembly Lot Number
G = Pb−Free Microdot
C9A = Specific Device Code
A = Assembly Location
Y = Production Year
W = Production Week
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CAT24C512
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Ratings
–65 to +150
Units
°C
Voltage on any Pin with Respect to Ground (Note 1)
–0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min Units
NEND (Notes 3, 4)
Endurance
1,000,000
Program/Erase Cycles
TDR Data Retention
100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re-programmed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min Max
Units
ICCR
Read Current
Read, fSCL = 400 kHz/1 MHz
1 mA
ICCW
Write Current
VCC = 1.8 V
1.8 mA
VCC = 5.5 V
2.5
ISB Standby Current
All I/O Pins at GND or VCC
TA = −40°C to +85°C
2 mA
TA = −40°C to +125°C
5
IL I/O Pin Leakage
Pin at GND or VCC
TA = −40°C to +85°C
1 mA
TA = −40°C to +125°C
2
VIL1 Input Low Voltage
2.5 V VCC 5.5 V
−0.5
0.3 VCC
V
VIL2 Input Low Voltage
1.8 V VCC < 2.5 V
−0.5
0.25 VCC
V
VIH1
Input High Voltage
2.5 V VCC 5.5 V
0.7 VCC
VCC + 0.5
V
VIH2
Input High Voltage
1.8 V VCC < 2.5 V
0.75 VCC
VCC + 0.5
V
VOL1
Output Low Voltage
VCC 2.5 V, IOL = 3.0 mA
0.4 V
VOL2
Output Low Voltage
VCC < 2.5 V, IOL = 1.0 mA
0.2 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN IMPEDANCE CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.
Symbol
Parameter
Conditions
Max
Units
CIN (Note 5)
SDA I/O Pin Capacitance
VIN = 0 V
8 pF
CIN (Note 5)
Input Capacitance (other pins)
VIN = 0 V
6 pF
IWP, IA (Note 6)
WP Input Current, Address Input
Current (A0, A1, A2)
VIN < VIH, VCC = 5.5 V
VIN < VIH, VCC = 3.3 V
75 mA
50
VIN < VIH, VCC = 1.8 V
25
VIN > VIH
2
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
6. When not driven, the WP, A0, A1, A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
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CAT24C512
Table 5. A.C. CHARACTERISTICS (Note 7)
VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.
Standard
VCC = 1.8 V − 5.5 V
Fast
VCC = 1.8 V − 5.5 V
Fast−Plus
VCC = 2.5 V − 5.5 V
TA = −405C to +855C
Symbol
Parameter
Min Max Min Max Min Max
FSCL
Clock Frequency
100 400 1,000
tHD:STA
START Condition Hold Time
4
0.6 0.25
tLOW
Low Period of SCL Clock
4.7
1.3 0.45
tHIGH
High Period of SCL Clock
4
0.6 0.40
tSU:STA
START Condition Setup Time
4.7
0.6 0.25
tHD:DAT
Data In Hold Time
0
0
0
tSU:DAT
Data In Setup Time
250
100
50
tR (Note 8)
SDA and SCL Rise Time
1,000
300
100
tF (Note 8)
SDA and SCL Fall Time
300 300 100
tSU:STO
STOP Condition Setup Time
4
0.6 0.25
tBUF
Bus Free Time Between
4.7
1.3
0.5
STOP and START
tAA SCL Low to Data Out Valid 3.5 0.9 0.40
tDH Data Out Hold Time
50
50
50
Ti (Note 8)
Noise Pulse Filtered at SCL
50
50
50
and SDA Inputs
tSU:WP
WP Setup Time
0
0
0
tHD:WP
WP Hold Time
2.5
2.5
1
tWR Write Cycle Time
555
tPU (Notes 8, 9) Power-up to Ready Mode 1 1 0.1 1
7. Test conditions according to “A.C. Test Conditions” table.
8. Tested initially and after a design or process change that affects this parameter.
9. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
0.2 x VCC to 0.8 x VCC
50 ns
Input Reference Levels
Output Reference Levels
Output Load
0.3 x VCC, 0.7 x VCC
0.5 x VCC
Current Source: IL = 3 mA (VCC 2.5 V); IL = 1 mA (VCC < 2.5 V); CL = 100 pF
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
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