BD9997FVT Datasheet PDF - Rohm


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BD9997FVT
Rohm

Part Number BD9997FVT
Description Silicon monolithic integrated circuits
Page 5 Pages

BD9997FVT datasheet pdf
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Structure
Silicon monolithic integrated circuits
Product Name
Model Name
Boost DC/DC converter LSI for Blu-ray
BD9997FVT
Function
(1) The output voltage can be set by external resistance.
(2) Internal Power MOS transistor with Backgate Control function
(3) Inrush current reduction
(4) Integrated Soft start
(5) Built-in Protection function
NMOS overcurrent limit, overvoltage mute,
thermal shutdown, output ground short protection
(6) UVLO operation at low power-supply voltage
(7) Easy assembly small sized package TSSOP-B8
(8) Built-in Discharge function
(9) function of output interception(at shutdown, at overvoltage)
○Absolute maximum ratings (Ta=25℃)
Item
Symbol
Limit
Supply voltage
Vcc -0.3~7
Power dissipation (※1)
Pd 0.625
Operating temperature range
Topt -25~+85
Storage temperature range
Tstg -55~+150
Input voltage range on SW
VINSW
-0.3~15
Input voltage range on VOUT
VINOUT
-0.3~15
Input voltage range on FB
VINFB
-0.3~VCC+ 0.3
AMPOUT terminal maximum input voltage
VINAMPOUT
-0.3~VCC+ 0.3
XSHDN terminal maximum input voltage
Junction temperature
VINSHDN
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Tjmax
-0.3~VCC+ 0.3
+150
(※1) While mounted on Glass-expoxy board(ROHM standard board:70×70×1.6[mm3])
○Operating conditions (Ta=25℃)
Item
Symbol
Min. Typ.
Supply voltage
Vcc 4.5 5.0
Output current1 (※2)(※5)
Iout1
--
Output current2 (※3)(※5)
Iout2
--
Output current3 (※4)(※5)
Iout3
--
(※2) VIN=4.5[V] → VOUT=7.5[V] (L=22[uH]) (※3) VIN=4.5[V] → VOUT=11.0[V] (L=22[uH])
(※4) VIN=4.5[V] → VOUT=8.1[V] (L=10[uH]) (※5) Do not, however exceed Pd.
Max.
5.5
0.15
0.10
0.20
1/4
Unit
V
W
V
V
V
V
V
Unit
V
A
A
A
REV. B
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Electric Characteristics Unless otherwise specified, Vcc=5.0[V], VOUT=5.0[V], Ta=25[]
Parameter
Symbol
Current consumption
Current consumption
Current consumption
(Shutdown mode)
Output voltage range
Soft start beginning time
ERRVREF voltage
Oscillator frequency
Maximum duty cycle
AMPOUT maximum
output voltage
AMPOUT minimum
output voltage
PMOS ON resistance
NMOS ON resistance
UVLO detection voltage
UVLO return voltage
XSHDN
Input threshold voltage
XSHDN pull down resister
ICC1
ICC2
ICC3
VOUTR
TSOFT
ERRVREF
SAWO
DMAX
VAMPOUTH
VAMPOUTL
RONP
RONN
VUVLO1
VUVLO2
VthXSHDN
RXSHDN
Limit
Min. Typ.
4.0 6.3
2.3 3.7
Vcc
3.5
0.582
400
65
2.00
1
6.0
0.600
650
80
2.30
0.36
0.30
3.35
3.45
0.92
7.0
0.03
0.60
0.50
3.55
3.65
1.53
10.0
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Max.
9.5
5.2
10
12.0
8.5
0.618
900
90
2.60
0.20
0.84
0.70
3.75
3.85
2.14
13.0
Unit Condition
mA
VCC=5.0[V], FB=2.5[V],
No load
mA
VCC=5.0[V], FB=0[V],
No load
μA
VCC=5.0[V],
XSHDN=GND or Open
V
ms VCC=5.0[V], FB=0[V]
V
kHz
%
V
V
Ω VOUT=9.0[V]
Ω VOUT=9.0[V]
V VCC Falling
V VCC Rising
V
kΩ
2/4
REV. B
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Package outline
3.0±0.1
Max 3.35 (include. BURR)
8 765
4°±4°
3/4
1
0.525
234
1Pin MARK
0.65
0.08
+0.05
0.245 -0.04
0.08
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+0.05
0.145 -0.03
LOT NO.
(UNIT: mm)
Block Diagram
VOUT
1
FB
2
BACKGATE
CONTROL
OUTPUT
CONTROL
CURRENT
LIMIT
AMPOUT
3
GND
4
ERRVREF
DTC
SOFT
START
SAW
SW
8
PGND
7
VCC
6
XSHDN
5
Terminal No./Terminal name
Terminal No
1
2
3
4
5
6
7
8
Terminal name
VOUT
FB
AMPOUT
GND
XSHDN
VCC
PGND
SW
REV. B
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4/4
Operation Notes
1About grand potential
Set PGND and GND to equal potential.The ground line is where the lowest potential and transient voltages are connected to
the IC.
2About starting
Keep light Load at VOUT output while start-up.
3About board pattern
Use separates ground lines for small control signals and high current outputs. Because these high current outputs that
flows to the wire impedance changes the GND voltage for control signal. Therefore each ground of IC must be connected at
one point on the set circuit board. As for GND of external parts, it’s similar to the above-mentioned. The characteristics of
DC/DC converter might influenced by surrounding components and board pattern. Consider the effects from surroundings
while design. Make VCC,PGND and GND impedance sufficiently low Solder RESERVE to GND on set circuit board.
4About peripheral circuit
Bypass capacitor between power supply and ground should be use low ESR ceramic capacitor and placed close to
the IC pin as possible. External components such as L and C is necessary to be placed as near to the IC as
possible with shortest distance. Monitor the output voltage at both end of capacitor connected to VOUT.PMOS
over current limit must not be built into, and the over current must not flow to PMOS. please have safe
countermeasure such as adding POLY SWITCH and fuse to avoid from over stressing.
5About absolute maximum rating
Exceeding supply voltage and operating Temp. over Absolute Maximum Ratings may cause degradation of IC and
even may destroy the IC. If special mode such that exceeding Absolute Maximum Ratings is expected, please have
safe countermeasure such as adding POLY SWITCH and fuse to avoid from over stressing.
6About heat design
Do not exceed the power dissipation (PD) of the package specification rating under actual operation.
7About Short between terminals and the mis-installation
While mounting IC on the board, check direction and positionwww.DataSheet.net/ of the IC. If inadequately mounted, the IC may destroy.
Moreover this IC might be destroyed when dust short the terminals between pins or pin and ground.
8About operation in strong electromagnetic field
Strong electromagnetic radiation can cause operation failures.
9About heat interception circuit (TSD)
The TSD is activated when the junction temperature (Tj) reaches 175and the output terminal is switched to Hi-Z. The
TSD circuit aims to intercept IC from high temperature. The guarantee and protection of IC are not purpose. Therefore,
please do not use this IC after TSD circuit operates, nor use it for assumption that operates the TSD circuit.
10About inspection by set substrate
The stress might hang to IC by connecting the capacitor to the terminal with low impedance. Then, please discharge
electricity in each and all process. Moreover, in the inspection process, please turn off the power before mounting the IC, and
turn on after mounting the IC. In addition, please take into consideration the countermeasures for electrostatic damage, such
as giving the earth in assembly process, transportation or preservation.
11About each input terminal
This IC is a monolithic IC, and has P+ isolation and P substrate for the element separation. Therefore, a parasitic PN junction
is firmed in this P-layer and N-layer of each element. When the GND voltage potential is greater than the voltage potential at
Terminals A or B, the PN junction operates as a parasitic diode. In addition, the parasitic NPN transistor is formed in said
parasitic diode and the N layer of surrounding elements close to said parasitic diode. These parasitic elements are formed in
the IC because of the voltage relation. The parasitic element operating causes the wrong operation and destruction.
Therefore, please be careful so as not to operate the parasitic elements by impressing to input terminals lower voltage than
GND (P substrate). Please do not apply the voltage to the input terminal when the power –supply voltage is not impressed.
Moreover, please impress each input terminal lower than the power-supply voltage or equal to the specified range in the
guaranteed voltage when the power-supply voltage is impressing..
REV. B
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