AZC199-02S Datasheet PDF - Amazing Microelectronic

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AZC199-02S
Amazing Microelectronic

Part Number AZC199-02S
Description Low Capacitance ESD Protection Array
Page 8 Pages


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AZC199-02S
Low Capacitance High ESD Level Protection Array
For High Speed I/O Port
Features
z ESD Protect for 2 high-speed I/O lines
z Provide ESD protection for each line to
IEC 61000-4-2,(ESD) (contact/air) ±16kV
IEC 61000-4-4 (EFT) Level-3, 55A (5/50ns)
IEC 61000-4-5 (Lightning) 5A (8/20μs)
z For low operating voltage applications: 5V,
4.2V, 3.3V, 2.5V etc.
z Low capacitance : 1.6pF typical
z Fast turn-on and Low clamping voltage
z Array of ESD rated diodes with internal
equivalent TVS diode
z Solid-state silicon-avalanche and active circuit
triggering technology
z Green part
Applications
z Video Graphics Cards
z Digital Visual Interface (DVI)
z USB2.0 Power and Data lines protection
z Notebook and PC Computers
z Monitors and Flat Panel Displays
Circuit Diagram
12
Description
AZC199-02S is a design which includes ESD
rated diode arrays to protect high speed data
interfaces. The AZC199-02S has been
specifically designed to protect sensitive
components which are connected to data and
transmission lines from over-voltage caused by
Electrostatic Discharging (ESD).
AZC199-02S is a unique design which includes
ESD rated, low capacitance steering diodes and
a unique design of clamping cell which is an
equivalent TVS diode in a single package. During
transient conditions, the steering diodes direct
the transient to ground line. The internal unique
design of clamping cell prevents over-voltage on
the data line, protecting any downstream
components.
AZC199-02S may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(±15kV air, ±8kV contact discharge).
Pin Configuration
GND
3
3
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I/O I/O
JEDEC SOT23-3L (Top View)
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AZC199-02S
Low Capacitance High ESD Level Protection Array
For High Speed I/O Port
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
PARAMETER
RATING
Peak Pulse Current (tp =8/20μs)
IPP
5
Operating Supply Voltage
ESD per IEC 61000-4-2 (Air/Contact)
VDC
VESD
6
±16
Lead Soldering Temperature
TSOL
260 (10 sec.)
Operating Temperature
Storage Temperature
TOP
TSTO
-55 to +85
-55 to +150
DC Voltage at any I/O pin
VIO (GND – 0.5) to (VDD + 0.5)
UNITS
A
V
kV
oC
oC
oC
V
PARAMETER
Leakage Current
Reverse Breakdown
Voltage
Forward Voltage
ESD Clamping
Voltage
ESD Dynamic Turn on
Resistance
Lightning Clamping
Voltage
Channel Input
Capacitance
Channel to Channel
Input Capacitance
Variation of Channel
Input Capacitance
ELECTRICAL CHARACTERISTICS
SYMBOL
CONDITIONS
ILeak
Vpin1 or pin2 = 5V, VPin3 = 0V, T=25 oC
MIN TYP MAX UNITS
1 μA
VBV IBV = 1mA, T=25 oC, Pin 1/2 to Pin 3
7
10 V
VF
Vclamp
Rdynamic
Vlightning
CIN
CCROSS
CIN
IF = 15mA, T=25 oC, Pin 3 to Pin1/2
IEC 61000-4-2 +6kV, T=25 oC, Contact
mode, Pin 1/2 to Pin 3
IEC 61000-4-2 0~+6kV,T=25 oC, Contact
mode, Pin 1/2 to Pin 3
IPP=5A, tp=8/20μs, T=25 oC
Pin 1/2 to Pin 3
Vpin3=0V,Vpin1 or 2=2.5V, f=1MHz,T=25oC,
Pin 1/2 to Pin 3
Vpin3 =0V, Vpin1 or 2=2.5V, f=1MHz,
T=25oC, Between Pin 1 and Pin 2
Vpin3 =0V, Vpin1 or 2=2.5V, f=1MHz,
T=25oC, (Pin 1 to Pin 3)–(Pin 2 to Pin 3)
0.85 1.1
11
V
V
0.3 Ω
8.5 V
1.6 1.9 pF
0.23 0.28 pF
0.06 0.08 pF
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AZC199-02S
Low Capacitance High ESD Level Protection Array
For High Speed I/O Port
Typical Characteristics
2.4 Typical Variation of CIN vs. VIN
2.1
1.8
1.5
1.2
0.9
0.6
f = 1MHz, T=25 oC,
0.3
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Input Voltage (V)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.0
Typical Variation of CIO-to-IO vs. VIN
f = 1MHz, T=25 oC,
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Input Voltage (V)
5.0
12
11
10
9
8
7
6
5
4
3
2
1
0
4.5
Clamping Voltage vs. Peak Pulse Current
Waveform
Parameters:
tr=8μs
td=20μs
5.0 5.5 6.0 6.5
Peak pulse Current (A)
7.0
Forward Clamping Voltage vs. Peak Pulse Current
5
4
3
2
Waveform
1
Parameters:
tr=8μs
td=20μs
0
4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
Peak pulse Current (A)
Transmission Line Pulsing (TLP) Measurement
18
16
14
12
10
8
6
V_pulse
Pulse from a
transmission line
100ns
TLP_I
+
TLP_V DUT
-
4
I/O to GND
2
0
0 2 4 6 8 10 12
Transmission Line Pulsing (TLP) Voltage (V)
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AZC199-02S
Low Capacitance High ESD Level Protection Array
For High Speed I/O Port
Applications Information
The AZC199-02S is designed to protect two lines
against System ESD/EFT/Lightning pulses by
clamping them to an acceptable reference.
The usage of the AZC199-02S is shown in Fig. 1.
Protected lines, such as data lines, control lines,
or power lines, are connected at pin 1 and 2. The
pin 3 should be connected directly to a ground
plane on the board. All path lengths connected to
the pins of AZC199-02S should be kept as short
as possible to minimize parasitic inductance in
the board traces.
In order to obtain enough suppression of ESD
induced transient, good circuit board is critical.
Thus, the following guidelines are recommended:
z Minimize the path length between the
protected lines and the AZC199-02S.
z Place the AZC199-02S near the input
terminals or connectors to restrict transient
coupling.
z The ESD current return path to ground
should be kept as short as possible.
z Use ground planes whenever possible.
z NEVER route critical signals near board
edges and near the lines which the ESD
transient easily injects to.
High
Speed IO
Ports
VDD
data-1
data-2
Control-1
GND
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Fig. 1
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