AZC015-02N Datasheet PDF - Amazing Microelectronic

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AZC015-02N
Amazing Microelectronic

Part Number AZC015-02N
Description Low Capacitance ESD Protection Array
Page 10 Pages


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AZC015-02N
Low Capacitance ESD Protection Array
For High Speed Data Interfaces
Features
z ESD Protect for 2 high-speed I/O channels
z Provide ESD protection for each channel to
IEC 61000-4-2 (ESD) ±18kV (air), ±14kV (contact)
IEC 61000-4-4 (EFT) (5/50ns) Level-3, 20A for I/O,
80A for Power
IEC 61000-4-5 (Lightning) 6.5A (8/20μs)
z 5V operating voltage
z Low capacitance : 1.3pF typical
z Fast turn-on and Low clamping voltage
z Array of surge rated diodes with internal
equivalent TVS diode
z Small package saves board space
z Solid-state silicon-avalanche and active circuit
triggering technology
Applications
z USB2.0 Power and Data lines protection
z Notebook and PC Computers
z Monitors and Flat Panel Displays
z IEEE 1394 Firewire Ports
z Video Graphics Cards
z SIM ports
Description
AZC015-02N is a high performance and low cost
design which includes surge rated diode arrays
to protect high speed data interfaces. The
AZC015-02N family has been specifically
designed to protect sensitive components, which
are connected to data and transmission lines,
from over-voltage caused by Electrostatic
Discharging (ESD), Electrical Fast Transients
(EFT), and Lightning.
AZC015-02N is a unique design which includes
surge rated, low capacitance steering diodes and
a unique design of clamping cell which is an
equivalent TVS diode in a single package. During
transient conditions, the steering diodes direct
wwwt.hDeattarSahnesetie4Un.tcotomeither the power supply line or to
the ground line. The internal unique design of
clamping cell prevents over-voltage on the power
line, protecting any downstream components.
AZC015-02N may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(± 15kV air, ±8kV contact discharge).
Circuit Diagram
4
2
1
3
Pin Configuration
VDD
4
I/O 2
3
1
GND
2
I/O 1
JEDEC SOT143-4L (Top View)
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AZC015-02N
Low Capacitance ESD Protection Array
For High Speed Data Interfaces
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
PARAMETER
RATING
Peak Pulse Current (tp =8/20μs)
IPP 6.5
Operating Supply Voltage (VDD-GND)
ESD per IEC 61000-4-2 (Air)(I/O to GND)
ESD per IEC 61000-4-2 (Contact) (I/O to GND)
ESD per IEC 61000-4-2(Air)(VDD-GND)
ESD per IEC 61000-4-2(Contact) (VDD-GND)
Lead Soldering Temperature
VDC
VESD_I/O
VESD_VDD
TSOL
6
18
14
30
30
260 (10 sec.)
Operating Temperature
TOP -55 to +85
Storage Temperature
TSTO
-55 to +150
DC Voltage at any I/O pin
VIO (GND – 0.5) to (VDD + 0.5)
UNITS
A
V
kV
kV
oC
oC
oC
V
PARAMETER
Reverse Stand-Off
Voltage
Reverse Leakage
Current
ELECTRICAL CHARACTERISTICS
SYMBOL
CONDITIONS
VRWM
Pin 4 to pin 1, T=25 oC
MIN TYP MAX UNITS
5V
ILeak VRWM = 5V, T=25 oC, Pin 4 to pin 1
5 μA
Channel Leakage
Current
Reverse
Breakdown
ICH_Leak
VBV
VPin 4 = 5V, VPin 1 = 0V, T=25 oC,
VCH = 0 ~ 5V
IBV = 1mA, T=25 oC
Pin 4 to Pin 1
6
1 μA
9V
Voltage
Forward Voltage
VF IF = 15mA, T=25 oC
Pin 1 to Pin 4
0.8 1
V
Clamping Voltage
VCL IPP=5A, tp=8/20μs, T=25 oC
Any Channel pin to Ground
8.1 9
V
ESD Clamping
Voltage –I/O
Vclamp_io
IEC 61000-4-2 +6kV, T=25 oC,
Contact mode, Any Channel pin to
Ground
12.5
V
ESD Clamping
Voltage –VDD
Vclamp_VDD
IEC 61000-4-2 +6kV, T=25 oC,
Contact mode, VDD pin to Ground
9
V
ESD Dynamic
IEC 61000-4-2 0~+6kV, T=25 oC,
Turn-on
Resistance –I/O
Rdynamic_io
Contact mode, Any Channel pin to
Ground
0.35
Ω
ESD Dynamic
Turn-on
Resistance –VDD
Rdynamic_VDD
IEC 61000-4-2 0~+6kV, T=25 oC,
Contact mode, VDD pin to Ground
0.2
Ω
Channel Input
Capacitance
CIN
1VMpinH4 =z,5TV=,2V5pionC1 =,
0V,
Any
VIN = 2.5V, f
Channel pin
=
1.3 1.6 pF
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to Ground
Channel to
Channel Input
CCROSS
1VMpinH4 =z,5TV=,2V5pionC1 =,
0V, VIN = 2.5V,
Between
f
=
0.12 0.14 pF
Capacitance
Channel pins
Variation of
Channel Input
CIN
1VMpinH4 =z,5TV=,2V5pionC1 =,
0V, VIN = 2.5V,
Channel_x pin
f=
to
0.05 0.07 pF
Capacitance
Ground - Channel_y pin to Ground
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AZC015-02N
Low Capacitance ESD Protection Array
For High Speed Data Interfaces
Typical Characteristics
110
100
90
80
70
60
50
40
30
20
10
0
0
Power Derating Curve
25 50 75 100 125
Ambient Temperature, TA (oC)
150
Forward Voltage vs. Forward Current
4.0
3.5
3.0
2.5
2.0
1.5
1.0
I/O pin to GND pin
0.5
Waveform
Parameters:
tr=8μs
td=20μs
0.0
4.5
5.0 5.5 6.0 6.5 7.0
Peak pulse Current (A)
7.5
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
20
Typical Variation of CIN vs. Temp
VDD = 5V, GND = 0V, VIN = 2.5V, f = 1MHz,
40 60 80 100 120
Temperature (oC)
Transmission Line Pulsing (TLP) Measurement
18
16
14
12
10
V_pulse
Pulse from a
transmission line
100ns
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6
TLP_I
+
TLP_V DUT
-
4
VDD to GND
2
0
0 1 2 3 4 5 6 7 8 9 10
Transmission Line Pulsing (TLP) Voltage (V)
Revision 2008/10/14 ©2008-2009 Amazing Micro.
12
11
10
9
8
7
6
5
4
3
2
1
0
4.5
Clamping Voltage vs. Peak Pulse Current
I/O pin to GND pin
Waveform
Parameters:
tr=8μs
td=20μs
5.0 5.5 6.0 6.5 7.0
Peak pulse Current (A)
7.5
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
Typical Variation of CIN vs. VIN
VDD = 5V, GND = 0V, f = 1MHz, T=25 oC,
1234
Input Voltage (V)
5
Transmission Line Pulsing (TLP) Measurement
18
16
14
12
10
8
6
V_pulse
Pulse from a
transmission line
100ns
TLP_I
+
TLP_V DUT
-
4
I/O to GND
2
0
0 2 4 6 8 10 12 14
Transmission Line Pulsing (TLP) Voltage (V)
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AZC015-02N
Low Capacitance ESD Protection Array
For High Speed Data Interfaces
Applications Information
A. Design Considerations
The ESD protection scheme for system I/O
connector is shown in the Fig. 1. In Fig. 1, the
diodes D1 and D2 are general used to protect
data line from ESD stress pulse. If the power-rail
ESD clamping circuit is not placed between VDD
and GND rails, the positive pulse ESD current
(IESD1) will pass through the ESD current path1.
Thus, the ESD clamping voltage VCL of data line
can be described as follow:
VCL = Fwd voltage drop of D1 + supply voltage of
VDD rail + L1 × d(IESD1)/dt + L2 × d(IESD1)/dt
Where L1 is the parasitic inductance of data line,
and L2 is the parasitic inductance of VDD rail.
An ESD current pulse can rise from zero to its
peak value in a very short time. As an example, a
level 4 contact discharge per the IEC61000-4-2
standard results in a current pulse that rises from
zero to 30A in 1ns. Here d(IESD1)/dt can be
approximated by ΔIESD1/Δt, or 30/(1x10-9). So
just 10nH of total parasitic inductance (L1 and L2
combined) will lead to over 300V increment in
VCL! Besides, the ESD pulse current which is
directed into the VDD rail may potentially
damage any components that are attached to
that rail. Moreover, it is common for the forward
voltage drop of discrete diodes to exceed the
damage threshold of the protected IC. This is due
to the relatively small junction area of typical
discrete components. Of course, the discrete
diode is also possible to be destroyed due to its
power dissipation capability is exceeded.
The AZC015-02N has an integrated
power-rail ESD clamped circuit between VDD
and GND rails. It can successfully overcome
previous disadvantages. During an ESD event,
the positive ESD pulse current (IESD2) will be
directed through the integrated power-rail ESD
clamped circuit to GND rail (ESD current path2).
The clamping voltage VCL on the data line is
small and protected IC will not be damaged
because power-rail ESD clamped circuit offer a
low impedance path to discharge ESD pulse
current.
power-rail ESD
clamp ing circuit
+
Vp
_
AZC015-02N
I ESD2
D1
D2
L2
I ESD1
L 1 data line
VESD
+
V
_
CL
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ESD current path 1 (IESD1)
ESD current path 2 (IESD2)
VDD rail
Prote cte d
IC
GND rail
Fig. 1 Application of positive ESD pulse between data line and GND rail.
Revision 2008/10/14 ©2008-2009 Amazing Micro.
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