AZ100E111 Datasheet PDF - Arizona


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AZ100E111
Arizona

Part Number AZ100E111
Description 1:9 Differential Clock Driver
Page 2 Pages

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DATA SHEET
AZ10E111
ARIZONA MICROTEK, INC.
AZ100E111
1:9 Differential Clock Driver
FEATURES
Low Skew
Guaranteed Skew Spec
Differential Design
Enable
VBB Output
Extended 100E VEE Range of -4.2V to -5.46V
75kInternal Input Pulldown Resistors
Direct Replacement for Motorola MC10EL111 & MC100EL111
Manufactured Under License By Lucent Technologies
PACKAGE AVAILABILITY
SUFFIX DESCRIPTION
FN Plastic 28 PLCC
DESCRIPTION
The AZ10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It
accepts one signal input, which can be either differential or single-ended if the VBB output is used. The signal is
fanned-out to 9 identical differential outputs. An Enable input is also provided. A HIGH disables the device by
forcing all Q outputs LOW and all QN outputs HIGH.
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design
and layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process
control limits that ensure consistent tpd distributions from lot-to-lot. The net result is a dependable, guaranteed low
skew device.
To ensure that the tight skew specification is met, both sides of the differential output must be terminated
into 50, even if only one side is used. In most applications all nine differential pairs will be used and therefore
terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs
on the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps)
of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin.
VEE
ENN
Q0 Q0N Q1 VCCO Q1N
25 24 23 22 21
26
27
Q2 Q2N
20 19
18
17
Q3
Q3N
LOGIC SYMBOL
Q0
QON
IN
VCC
INN
28
1
2
Pinout: 28-Lead PLCC
(Top View)
16 Q4
15 VCCO
14 Q4N
Q1
Q1N
Q2
Q2N
VBB
NC
3
4
13 Q5
12 Q5N
5 6 7 8 9 10 11
IN
INN
ENN
Q3
Q3N
Q4
Q4N
Q8N
Q8 Q7N VCCO Q7 Q6N
Q6
PIN DESCRIPTION
PIN
IN, INN
ENN
Q0, Q0N-Q8N,
Q8
FUNCTION
Differential Input Pair
Enable
Differential Outputs
VBB Output
VBB
Q5
Q5N
Q6
Q6N
Q7
Q7N
Q8
Q8N
6/99



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AZ10E111
AZ100E111
DC Characteristics (VEE = 10E(-4.94V to -5.46V),100E(-4.2V to -5.46V); VCC = VCCO = GND)
-40°C
0°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
VBB
Reference Voltage 10E -1.43
100E -1.38
-1.30 -1.38
-1.26 -1.38
-1.27 -1.35
-1.26 -1.38
-1.25 -1.31
-1.26 -1.38
-1.19
-1.26
V
IIH Input HIGH Current
150 150 150 150 µA
IEE
Power Supply 10E
Current
100E
48 60
48 60
48 60
48 60
48 60
48 60
48
55
60
69
mA
VPP (DC)
VCMR
Input Sensitivity
Common Mode Range
50
-1.6
50
-0.4 -1.6
50
-0.4 -1.6
50
-0.4 -1.6
mV
-0.4 V
1. Differential input voltage required to obtain a full ECL swing on the outputs.
2. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must
be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP(min).
Cond
1
2
AC Characteristics (VEE = 10E(-4.94V to -5.46V),100E(-4.2V to -5.46V); VCC = VCCO = GND)
-40°C
0°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
Propagation Delay
tPLH
to Output
IN (Diff) 380
tPHL IN (SE) 280
Enable 400
680 460
780 410
900 450
560 480
610 430
850 450
580 510
630 460
850 450
610
660 ps
850
Disable 400
900 450
850 450
850 450
850
tS Setup Time ENN to IN 250 0
200 0
200 0
200 0
ps
th Hold Time IN to ENN 50 -200
0 -200
0 -200
0 -200
ps
tR Release Time ENN to IN 350 100
300 100
300 100
300 100
ps
tskew Within-Device Skew
25 75
25 50
25 50
25 50 ps
VPP (AC) Minimum Input Swing
250
250
250
250 mV
tr / tf Rise/Fall Time
250 450 650 275 375 600 275 375 600 275 375 600 ps
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
3. Enable is defined as the propagation delay from the 50% point of a negative transition on ENN to the 50% point of a positive transition on Q (or a
negative transition on QN). Disable is defined as the propagation delay from the 50% point of a positive transition on ENN to the 50% point of a
negative transition on Q (or a positive transition on QN).
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
5. The setup time is the minimum time that ENN must be asserted prior to the next transition of IN/INN to prevent an output response greater than ±75
mV to that IN/INN transition (see Figure 1).
6. The hold time is the minimum time that ENN must remain asserted after a negative going IN or a positive going INN to prevent an output response
greater than ±75 mV to that IN/INN transition (see Figure 2).
7. The release time is the minimum time that ENN must be deasserted prior to the next IN/INN transition to ensure an output response that meets the
specified IN to Q propagation delay and output transition times (see Figure 3).
8. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for
the E111, as a differential input as low as 50 mV will still produce full ECL levels at the output.
Cond
1
2
3
3
5
6
7
4
8
.ARIZONA MICROTEK, INC 225 E. FIRST ST., SUITE 107 MESA, AZ 85201-6700 (480) 962-5881 FAX (480) 890-2541
http://www.azmicrotek.com




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