ATR0630 Datasheet PDF - ATMEL Corporation

www.Datasheet-PDF.com

ATR0630
ATMEL Corporation

Part Number ATR0630
Description Single-chip GPS Receiver
Page 30 Pages


ATR0630 datasheet pdf
Download PDF
ATR0630 pdf
View PDF for Mobile

No Preview Available !

www.DataSheet4U.com
Features
16-channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (2D, Stand Alone)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –139 dBm (With External LNA)
– Tracking Sensitivity: –149 dBm (With External LNA)
Utilizes the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– Embedded ICE (In-Circuit Emulation)
128 Kbytes Internal RAM
384 Kbytes Internal ROM with u-blox GPS Firmware
1.5-bit ADC On-chip
Single IF Architecture
2 External Interrupts
24 User-programmable I/O Lines
1 USB Device Port
– Universal Serial Bus (USB) 2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
2 USARTs
Master/Slave SPI Interface
– 4 External Slave Chip Selects
Programmable Watchdog Timer
Advanced Power Management Controller (APMC)
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
Real Time Clock (RTC)
1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance
4 KBytes of Battery Backup Memory
7 mm × 10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant
Benefits
Fully Integrated Design With Low BOM
No External Flash Memory Required
Requires Only a GPS XTAL, No TCXO
Supports NMEA, UBX Binary and RTCM Protocol
Supports SBAS (WAAS, EGNOS, MSAS)
Up to 4Hz Update Rate
Supports A-GPS (Aiding)
Excellent Noise Performance
ANTARIS4
Single-chip
GPS Receiver
ATR0630
Preliminary
Rev. 4920A–GPS–01/06



No Preview Available !

www.DataSheet4U.com
1. Description
The ATR0630 is a low-power, single-chip GPS receiver, especially designed to meet the
requirements of mobile applications. It is based on Atmel’s ANTARIS4 technology and inte-
grates an RF front-end, filtering, and a baseband processor in a single, tiny 7 mm × 10 mm
96 pin BGA package. Providing excellent RF performance with low noise figure and low power
consumption.
Due to the fully integrated design, just an RF SAW filter, a GPS XTAL (no TCXO) and blocking
capacitors are required to realize a stand-alone GPS functionality.
The ATR0630 includes a complete GPS firmware, licensed from u-blox AG, which performs the
GPS operation, including tracking, acquisition, navigation and position data output. For normal
PVT (Position/Velocity/Time) applications, there is no need for external Flash- or ROM-memory.
The firmware supports the possibility to store the configuration settings in an optional external
EEPROM.
Due to the integrated ARM7TDMI processor and an intelligent radio architecture, the ATR0630
operates in a complete autonomous mode, utilizing on chip AGC in closed loop operation.
For maximum performance, we recommend to use the ATR0630 together with a low noise
amplifier (e.g. ATR0610).
The ATR0630 supports assisted GPS.
2 ATR0630 [Preliminary]
4920A–GPS–01/06



No Preview Available !

www.DataSheet4U.com
2. Architectural Overview
2.1 Block Diagram
Figure 2-1. ATR0630 Block Diagram
PUXTO
PURF
VDD18
VDDIO
VDD_USB
VDIG
VCC1
VCC2
VBP
TEST
MO
RF
NRF
XTO
NXTO
X
NX
RF_ON
NSHDN
NSLEEP
XT_IN
XT_OUT
P20/TIMEPULSE
P29/GPSMODE12
P27/GPSMODE11
P26/GPSMODE10
P24/GPSMODE8
P23/GPSMODE7
P19/GPSMODE6
P17/GPSMODE5
P13/GPSMODE3
P12/GPSMODE2
P1/GPSMODE0
P14/NAADET1
P25/NAADET0
P15/ANTON
P0/NANTSHORT
P9/EXTINT0
P16/NEEPROM
VCO
PLL
XTO
ATR0630 [Preliminary]
Power Supply Manager/
PMSS/Logic
1
A
D
A
D
VBAT18
VBAT
LDOBAT_IN
LDO_OUT
LDO_IN
LDO_EN
AGCO
EGC
SDI
SIGHI
SIGLO
CLK23
P21/TXD2
P22/RXD2
P18/TXD1
P31/RXD1
USB_DP
USB_DM
P8/STATUSLED
P30/AGCOUT0
P2/BOOT_MODE
4920A–GPS–01/06
DBG_EN
NTRST
TDI
TDO
TCK
TMS
NRESET
3



No Preview Available !

www.DataSheet4U.com
2.2 General Description
The ATR0630 has been designed especially for mobile applications. It provides high isolation
between GPS and cellular bands, as well as very low power consumption.
ATR0630 is based on the successful ANTARIS4 technology which includes the ANTARIS ROM
software, developed by u-blox AG, Switzerland. ANTARIS provides a proven navigation engine
which is used in high-end car navigation systems, automatic vehicle location (AVL), security and
surveying systems, traffic control, road pricing, and speed camera detectors, and provides loca-
tion-based services (LBS) worldwide.
The ANTARIS4 chipset has a very low power consumption and comes with a very low BoM for
the passive components. Especially, due to its fast search engine and GPS accelerator, the
ATR0630 only needs a GPS crystal (XTAL) as a resonator for the integrated crystal oscillator of
the ATR0630. This saves the considerable higher cost of a TCXO which is required for competi-
tor’s systems. Also, as the powerful standard software is available in ROM, no external flash
memory is needed.
The L input signal (fRF) is a Direct Sequence Spread Spectrum (DSSS) signal with a center fre-
quency of 1575.42 MHz. The digital modulation scheme is Bi-Phase-Shift-Keying (BPSK) with a
chip rate of 1.023 Mbps.
2.3 PMSS Logic
The power management, startup and shutdown (PMSS) logic ensures reliable operation within
the recommended operating conditions. The external power control signals PUrf and PUxto are
passed through Schmitt trigger inputs to eliminate voltage ripple and prevent undesired behavior
during start-up and shut-down. Digital and analog supply voltages are analyzed by a monitoring
circuit, enabling the startup of the IC only when it is within a safe operating range.
2.4 XTO
The XTO is designed for minimum phase noise and frequency perturbations. The balanced
topology gives maximum isolation from external and ground coupled noise. The built-in jump
start circuitry ensures reliable start-up behavior of any specified crystal. For use with an external
TCXO, the XTO circuitry can be used as a single-ended or balanced input buffer.
The recommended reference frequency is: fXTO = 23.104 MHz.
2.5 VCO/PLL
The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no
external components are required. The VCO combines very good phase noise behavior and
excellent spurious suppression. The relation between the reference frequency (fXTO) and the
VCO center frequency (fVCO) is given by: fVCO = fXTO × 64 = 23.104 MHz × 64 = 1478.656 MHz.
2.6 RF Mixer/Image Filter
Combined with the antenna, an external LNA provides a first band-path filtering of the signal.
Atmel’s ATR0610 is recommended for the LNA due to its low noise figure, high linearity and low
power consumption. The output of the LNA drives a SAW filter, which provides image rejection
for the mixer and the required isolation to all GSM bands. The output of the SAW filter is fed into
a highly linear mixer with high conversion gain and excellent noise performance.
4 ATR0630 [Preliminary]
4920A–GPS–01/06



ATR0630 datasheet pdf
Download PDF
ATR0630 pdf
View PDF for Mobile


Related : Start with ATR063 Part Numbers by
ATR0630 Single-chip GPS Receiver ATR0630
ATMEL Corporation
ATR0630 pdf
ATR0635 Single-Chip GPS Receiver Supersense ATR0635
ATMEL Corporation
ATR0635 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact