ATMEGA32U2 Datasheet PDF - ATMEL

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ATMEGA32U2
ATMEL

Part Number ATMEGA32U2
Description 8-bit Microcontroller
Page 30 Pages


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Features
High Performance, Low Power AVR® 8-Bit Microcontroller
Advanced RISC Architecture
– 125 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
Non-volatile Program and Data Memories
– 8K/16K/32K Bytes of In-System Self-Programmable Flash
– 512/512/1024 EEPROM
– 512/512/1024 Internal SRAM
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85C/ 100 years at 25C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by on-chip Boot Program hardware-activated after
reset
True Read-While-Write Operation
– Programming Lock for Software Security
USB 2.0 Full-speed Device Module with Interrupt on Transfer Completion
– Complies fully with Universal Serial Bus Specification REV 2.0
– 48 MHz PLL for Full-speed Bus Operation : data transfer rates at 12 Mbit/s
– Fully independant 176 bytes USB DPRAM for endpoint memory allocation
– Endpoint 0 for Control Transfers: from 8 up to 64-bytes
– 4 Programmable Endpoints:
IN or Out Directions
Bulk, Interrupt and IsochronousTransfers
Programmable maximum packet size from 8 to 64 bytes
Programmable single or double buffer
– Suspend/Resume Interrupts
– Microcontroller reset on USB Bus Reset without detach
– USB Bus Disconnection on Microcontroller Request
Peripheral Features
– One 8-bit Timer/Counters with Separate Prescaler and Compare Mode (two 8-bit
PWM channels)
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Mode
(three 8-bit PWM channels)
– USART with SPI master only mode and hardware flow control (RTS/CTS)
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
On Chip Debug Interface (debugWIRE)
Special Microcontroller Features
– Power-On Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby
I/O and Packages
– 22 Programmable I/O Lines
– QFN32 (5x5mm) / TQFP32 packages
Operating Voltages
– 2.7 - 5.5V
Operating temperature
– Industrial (-40°C to +85°C)
Maximum Frequency
– 8 MHz at 2.7V - Industrial range
– 16 MHz at 4.5V - Industrial range
Note: 1. See “Data Retention” on page 6 for details.
8-bit
Microcontroller
with
8/16/32K Bytes
of ISP Flash
and USB
Controller
ATmega8U2
ATmega16U2
ATmega32U2
7799E–AVR–09/2012



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1. Pin Configurations
Figure 1-1. Pinout
ATmega8U2/16U2/32U2
XTAL1
(PC0) XTAL2
GND
VCC
(PCINT11 / AIN2 ) PC2
(OC.0B / INT0) PD0
(AIN0 / INT1) PD1
(RXD1 / AIN1 / INT2) PD2
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4
5
QFN32
21
20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
Reset (PC1 / dW)
PC6 (OC.1A / PCINT8)
PC7 (INT4 / ICP1 / CLKO)
PB7 (PCINT7 / OC.0A / OC.1C)
PB6 (PCINT6)
PB5 (PCINT5)
PB4 (T1 / PCINT4)
PB3 (PDO / MISO / PCINT3)
XTAL1
(PC0) XTAL2
GND
VCC
(PCINT11 /AIN2 ) PC2
(OC.0B / INT0) PD0
(AIN0 / INT1) PD1
(RXD1 / AIN1 / INT2) PD2
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4
5
TQFP32
21
20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
Reset (PC1 / dW)
PC6 (OC.1A / PCINT8)
PC7 (INT4 / ICP1 / CLKO)
PB7 (PCINT7 / OC.0A / OC.1C)
PB6 (PCINT6)
PB5 (PCINT5)
PB4 (T1 / PCINT4)
PB3 (PDO / MISO / PCINT3)
Note: The large center pad underneath the QFN package should be soldered to ground on the board to
ensure good mechanical stability.
1.1 Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
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ATmega8U2/16U2/32U2
2. Overview
The ATmega8U2/16U2/32U2 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture.
By executing powerful instructions in a single clock cycle, the ATmega8U2/16U2/32U2 achieves throughputs approaching
1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
PD7 - PD0
PC7 - PC0
PB7 - PB0
PORTD DRIVERS
PORTC DRIVERS
PORTB DRIVERS
VCC
GND
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
DATA REGISTER
PORTB
8-BIT DA TA BUS
DATA DIR.
REG. PORTB
Debug-Wire
POR - BOD
RESET
PROGRAM
COUNTER
STACK
POINTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
CALIB. OSC
OSCILLATOR
ON-CHIP DEBUG
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
TIMING AND
CONTROL
PROGRAMMING
LOGIC
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
USART1
SPI
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
PLL
USB
PS/2
ON-CHIP
3.3V
REGULATOR
UVcc
UCap
1uF
D+/SCK
D-/SDATA
7799E–AVR–09/2012
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
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ATmega8U2/16U2/32U2
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega8U2/16U2/32U2 provides the following features: 8K/16K/32K Bytes of In-System
Programmable Flash with Read-While-Write capabilities, 512/512/1024 Bytes EEPROM,
512/512/1024 SRAM, 22 general purpose I/O lines, 32 general purpose working registers, two
flexible Timer/Counters with compare modes and PWM, one USART, a programmable Watch-
dog Timer with Internal Oscillator, an SPI serial port, debugWIRE interface, also used for
accessing the On-chip Debug system and programming and five software selectable power sav-
ing modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port,
and interrupt system to continue functioning. The Power-down mode saves the register contents
but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware
Reset. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device
is sleeping. This allows very fast start-up combined with low power consumption. In Extended
Standby mode, the main Oscillator continues to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The on-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an on-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega8U2/16U2/32U2 is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control applications.
The ATmega8U2/16U2/32U2 are supported with a full suite of program and system develop-
ment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators, and evaluation kits.
2.2 Pin Descriptions
2.2.1 VCC
Digital supply voltage.
2.2.2 GND
Ground.
2.2.3 AVCC
AVCC is the supply voltage pin (input) for all analog features (Analog Comparator, PLL). It
should be externally connected to VCC through a low-pass filter.
2.2.4
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega8U2/16U2/32U2 as
listed on page 74.
7799E–AVR–09/2012
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