ATF-531P8 Datasheet PDF - AVAGO

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ATF-531P8
AVAGO

Part Number ATF-531P8
Description High Linearity Enhancement Mode Pseudomorphic HEMT
Page 15 Pages


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ATF-531P8
High Linearity Enhancement Mode[1] ­Pseudomorphic HEMT
in 2x2 mm2 LPCC[3] ­Package
Data Sheet
Description
Avago Technologies’ ­­ATF‑531P8 is a single-voltage high
linearity, low noise E‑pHEMT housed in an 8-lead JEDEC-
standard leadless plastic chip carrier (LPCC[3]) package.
The device is ideal as a high linearity, low-noise, medium-
power amplifier. Its operating frequency range is from 50
MHz to 6 GHz.
The thermally efficient package measures only 2 mm
x 2 mm x 0.75 mm. Its backside metalization provides
excellent thermal dissipation as well as visual evidence
of solder reflow. The device has a Point MTTF of over 300
years at a mounting temperature of +85°C. All devices are
100% RF & DC tested.
Pin Connections and Package Marking
Pin 8
Pin 7 (Drain)
Pin 6
Pin 5
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Bottom View
Pin 1 (Source)
Pin 8
Pin 2 (Gate)
Pin 3
3Px
Pin 7 (Drain)
Pin 6
Pin 4 (Source)
Top View
Pin 5
Note:
Package marking provides orientation and identification:
“3P” = Device Code
“x” = Date code indicates the month of manufacture.
Features
Single voltage operation
High linearity and gain
Low noise figure
Excellent uniformity in product specifications
Small package size:
2.0 x 2.0 x 0.75 mm
Point MTTF > 300 years[2]
MSL-1 and lead-free
Tape-and-reel packaging option available
Specifications
2 GHz; 4V, 135 mA (Typ.)
38 dBm output IP3
0.6 dB noise figure
20 dB gain
10.7 dB LFOM[4]
24.5 dBm output power at 1 dB gain compression
Applications
Front-end LNA Q1 and Q2 driver or pre-driver ampli‑
fier for Cellular/PCS and WCDMA wireless infrastruc‑
ture
Driver amplifier for WLAN, WLL/RLL and MMDS ap‑
plications
General purpose discrete E-pHEMT for other high
linearity applications
Notes:
1. Enhancement mode technology employs a single positive Vgs, eliminating the need of negative gate voltage associated with conventional
depletion mode devices.
2. Refer to reliability datasheet for detailed MTTF data.
3. Conforms to JEDEC reference outline MO229 for DRP-N
4. Linearity Figure of Merit (LFOM) is essentially OIP3 divided by DC bias power.



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ATF-531P8 Absolute Maximum Ratings[1]
Symbol
Parameter
Units
Absolute
Maximum
VDS
VGS
VGD
IDS
IGS
P
diss
Pin max.
TCH
TSTG
θch_b
Drain–Source Voltage[2]
Gate­–Source Voltage[2]
Gate Drain Voltage[2]
Drain Current[2]
Gate Current
Total Power Dissipation[3]
RF Input Power
Channel Temperature
Storage Temperature
Thermal Resistance[4]
V 7
V -7 to 1
V -7 to 1
mA 300
mA 20
W 1
dBm
+24
°C 150
°C -65 to 150
°C/W
63
Notes:
1. Operation of this device in excess of any one
of these parameters may cause permanent
damage.
2. Assumes DC quiescent conditions.
3. Board (package belly) temperatureTB is 25°C.
Derate 16 mW/°C for TB > 87°C.
4. Thermal resistance measured using
150°C Liquid Crystal Measurement meth‑
od.
5. Device can safely handle +24 dBm RF Input
Power provided IGS is limited to 20mA. IGS
at P1dB drive level is bias circuit depen‑
dent.
400
0.9 V
300
0.8 V
200 0.7 V
100 0.6 V
0
01 2 3 4
VDS (V)
Figure 1. Typical I-V Curves
(Vgs = 0.1 per step).
0.5 V
56
7
Product Consistency Distribution Charts at 2 GHz, 4V, 135 mA[5,6]
180 160
Cpk = 1.0
150 Stdev = 0.14
120
120
90 -3 Std
+3 Std
80 -3 Std
Cpk = 1.2
Stdev = 0.71
+3 Std
60
40
30
0
0 0.3 0.6
NF (dB)
Figure 2. NF
Nominal = 0.6, USL = 1.0.
0.9
1.2
0
35 36 37 38 39
OIP3 (dBm)
Figure 3. OIP3
LSL = 35.5, Nominal = 38.1.
40 41
300
Cpk = 2.0
250 Stdev = 0.21
200
150
-3 Std
+3 Std
100
50
0
18.5 19.5 20.5 21.5
GAIN (dB)
Figure 4. Small Signal Gain
LSL = 18.5, Nominal = 20.2 dB, USL = 21.5.
240
Stdev = 0.12
200
160
120 -3 Std
+3 Std
80
40
0
24.2 24.4 24.6 24.8
P1dB (dBm)
Figure 5. P1dB
Nominal = 24.6.
25 25.2
Notes:
5. Distribution data sample size is 500 samples taken from 5 different wafers and 3 different lots. Future wafers allocated to this product may
have nominal values anywhere between the upper and lower limits.
6. Measurements are made on production test board, which represents a trade-off between optimal OIP3, NF and VSWR. Circuit losses have
been de‑embedded from actual measurements.




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ATF-531P8 Electrical Specifications
TA = 25°C, DC bias for RF parameters is Vds = 4V and Ids = 135 mA unless otherwise specified.
Symbol
Parameter and Test Condition
Units Min. Typ.
Vgs Operational Gate Voltage Vds = 4V, Ids = 135 mA V — 0.68
Vth Threshold Voltage Vds = 4V, Ids = 8 mA
V — 0.3
Idss Saturated Drain Current Vds = 4V, Vgs = 0V
µA — 3.7
Gm Transconductance Vds = 4.5V, Gm = Idss/Vgs;
Vgs = Vgs1 - Vgs2
Vgs1 = 0.6V, Vgs2 = 0.55V
mmho
650
Igss Gate Leakage Current Vds = 0V, Vgs = -4V
µA -10 -0.34
NF Noise Figure[1] f = 2 GHz
f = 900 MHz
dB ­ — 0.6
dB — 0.6
G Gain[1] f = 2 GHz
f = 900 MHz
dB 18.5 20
dB — 25
OIP3
Output 3rd Order f = 2 GHz
Intercept Point[1,2] f = 900 MHz
dBm 35.5 38
dBm
37
P1dB
Output 1dB f = 2 GHz
Compressed[1] f = 900 MHz
dBm
dBm
24.5
23
PAE Power Added Efficiency f = 2 GHz
f = 900 MHz
% — 57
% — 45
ACLR
Adjacent Channel Leakage Offset BW = 5 MHz
Power Ratio[1,3] Offset BW = 10 MHz
Notes:
1. Measurements obtained using production test board described in Figure 6.
2. F1 = 2.00 GHz, F2 = 2.01 GHz and Pin = -10 dBm per tone.
3. ACLR test spec is based on 3GPP TS 25.141 V5.3.1 (2002-06)
– Test Model 1
– Active Channels: PCCPCH + SCH + CPICH + PICH + SCCPCH + 64 DPCH (SF=128)
– Freq = 2140 MHz
– Pin = -5 dBm
– Chan Integ Bw = 3.84 MHz
dBc
dBc
— -68
— -64
Max.
1
21.5
Input
50 Ohm
Transmission
Line Including
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
Γ_mag = 0.66
Γ_ang = -165°
(1.8 dB loss)
Output
Matching Circuit
DUT Γ_mag = 0.09
Γ_ang = 118°
(1.1 dB loss)
50 Ohm
Transmission
Line and
Drain Bias T
(0.3 dB loss)
Output
Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE and ACLR measurements. This circuit achieves a trade-
off between optimal OIP3, NF and VSWR. Circuit losses have been de-embedded from actual measurements.




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2.2 pF
RF Input
3.3 pF
50 Ohm
.02 λ
110 Ohm
.03 λ
22 nH
15 Ohm
DUT
100 pF
Gate
DC Supply
110 Ohm
.03 λ
50 Ohm
.02 λ
4.7 pF
RF Output
12 nH
2.2 µF
Drain
DC Supply
Figure 7. Simplified schematic of production test board. Primary purpose is to show 15 Ohm series resistor placement in gate supply. Transmis-
sion line tapers, tee intersections, bias lines and parasitic values are not shown.
Gamma Load and Source at Optimum OIP3 Tuning Conditions
The device’s optimum OIP3 measurements were determined using a Maury load pull system at 4V, 135 mA quiesent
bias. The gamma load and source over frequency are shown in the table below:
Freq
(GHz)
0.9
2.0
3.9
5.8
Gamma Source
Mag Ang
0.616 -37.1
0.310
34.5
0.421
167.5
0.402 -162.8
Gamma Load
Mag Ang
0.249
130.0
0.285
168.3
0.437 -161.6
0.418 -134.1
OIP3
(dBm)
40.3
41.5
41.5
41.0
Gain P1dB
(dB) (dBm)
16.5 23.4
13.4 24.8
10.5 24.7
7.9 24.7
PAE
(%)
43.2
51.9
42.8
36.6




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