ATF-511P8 Datasheet PDF - Agilent

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ATF-511P8
Agilent

Part Number ATF-511P8
Description Enhancement Mode Pseudomorphic HEMT
Page 16 Pages


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Agilent ATF-511P8 High Linearity
Enhancement Mode[1]
Pseudomorphic HEMT in
2x2 mm2 LPCC[3] Package
Data Sheet
Description
Agilent Technologies’s
ATF-511P8 is a single-voltage
high linearity, low noise
E-pHEMT housed in an 8-lead
JEDEC-standard leadless
plastic chip carrier (LPCC[3])
package. The device is ideal as
a high linearity, low-noise,
medium-power amplifier. Its
operating frequency range is
from 50 MHz to 6 GHz.
The thermally efficient package
measures only 2 mm x 2 mm x
0.75 mm. Its backside
metalization provides excellent
thermal dissipation as well as
visual evidence of solder reflow.
The device has a Point MTTF of
over 300 years at a mounting
temperature of +85°C. All
devices are 100% RF & DC tested.
Note:
1. Enhancement mode technology employs a
single positive Vgs, eliminating the need of
negative gate voltage associated with
conventional depletion mode devices.
2. Refer to reliability datasheet for detailed
MTTF data.
3. Conforms to JEDEC reference outline MO229
for DRP-N.
4. Linearity Figure of Merit (LFOM) is essentially
OIP3 divided by DC bias power.
Pin Connections and
Package Marking
Pin 8
Pin 7 (Drain)
Pin 6
Pin 5
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Bottom View
Pin 1 (Source)
Pin 8
Pin 2 (Gate)
Pin 3
1Px
Pin 7 (Drain)
Pin 6
Pin 4 (Source)
Pin 5
Top View
Note:
Package marking provides orientation and
identification:
“1P” = Device Code
“x” = Date code indicates the month of
manufacture.
Features
Single voltage operation
High linearity and P1dB
Low noise figure
Excellent uniformity in product
specifications
Small package size:
2.0 x 2.0 x 0.75 mm
Point MTTF > 300 years[2]
MSL-1 and lead-free
Tape-and-reel packaging option
available
Specifications
2 GHz; 4.5V, 200 mA (Typ.)
41.7 dBm output IP3
30 dBm output power at 1 dB gain
compression
1.4 dB noise figure
14.8 dB gain
12.1 dB LFOM[4]
69% PAE
Applications
Front-end LNA Q2 and Q3 driver or
pre-driver amplifier for Cellular/
PCS and WCDMA wireless
infrastructure
Driver amplifier for WLAN,
WLL/RLL and MMDS applications
General purpose discrete E-pHEMT
for other high linearity applications



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ATF-511P8 Absolute Maximum Ratings[1]
Symbol
VDS
VGS
VGD
IDS
IGS
Pdiss
Pin max.
TCH
TSTG
θch_b
Parameter
DrainSource Voltage[2]
GateSource Voltage[2]
Gate Drain Voltage[2]
Drain Current[2]
Gate Current
Total Power Dissipation[3]
RF Input Power[4]
Channel Temperature
Storage Temperature
Thermal Resistance[5]
Units
V
V
V
A
mA
W
dBm
°C
°C
°C/W
Absolute
Maximum
7
-5 to 1
-5 to 1
1
46
3
+30
150
-65 to 150
33
Notes:
1. Operation of this device in excess of any one
of these parameters may cause permanent
damage.
2. Assumes DC quiescent conditions.
3. Board (package belly) temperatureTB is 25°C.
Derate 30 mW/°C for TB > 50°C.
4. With 10 Ohm series resistor in gate supply
and 3:1 VSWR.
5. Channel-to-board thermal resistance
measured using 150°C Liquid Crystal
Measurement method.
6. Device can safely handle +30dBm RF Input
Power provided IGS limited to 46mA. IGS at
P1dB drive level is bias circuit dependent.
1000
900
800
700
600
500
400
300
200
100
0
02
4
VDS (V)
Figure 1. Typical I-V Curves
(Vgs = 0.1 per step).
0.8 V
0.7 V
0.6 V
0.5 V
68
Product Consistency Distribution Charts at 2 GHz, 4.5V, 200 mA[6,7]
240 200
Cpk = 1.66
Cpk = 3.24
200
Stdev = 0.6
160
Stdev = 0.15
160
-3 Std
+3 Std
120
80
120
80
-3 Std
+3 Std
40 40
0
35 38
41
OIP3 (dBm)
Figure 2. OIP3
LSL = 38.5, Nominal = 41.7.
44
47
0
28 29
30
P1dB (dBm)
Figure 3. P1dB
LSL = 28.5, Nominal = 30.
31
150
Cpk = 1.4
120 Stdev = 0.31
90
-3 Std
60
+3 Std
30
0
13 14 15 16
GAIN (dB)
17
Figure 4. Gain
LSL = 13.5, Nominal = 14.8, USL = 16.5.
160
Cpk = 3.03
Stdev = 1.85
120
80
-3 Std
+3 Std
40
0
52 57 62 67 72 77 82
PAE (%)
Figure 5. PAE
LSL = 52, Nominal = 68.9.
Notes:
6. Distribution data sample size is 400 samples taken from 4 different wafers and 3 different lots.
Future wafers allocated to this product may have nominal values anywhere between the upper and
lower limits.
7. Measurements are made on production test board, which represents a trade-off between optimal
OIP3, P1dB and VSWR. Circuit losses have been de-embedded from actual measurements.
2



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ATF-511P8 Electrical Specifications
TA = 25°C, DC bias for RF parameters is Vds = 4.5V and Ids = 200 mA unless otherwise specified.
Symbol
Parameter and Test Condition
Units
Min.
Typ.
Max.
Vgs Operational Gate Voltage
Vds = 4.5V, Ids = 200 mA
V
0.25 0.51 0.8
Vth Threshold Voltage
Vds = 4.5V, Ids = 32 mA
V
0.28
Idss Saturated Drain Current
Vds = 4.5V, Vgs = 0V
µA 16.4
Gm Transconductance
Vds = 4.5V, Gm = Idss/Vgs;
Vgs = Vgs1 Vgs2
Vgs1 = 0.55V, Vgs2 = 0.5V
mmho
2178
Igss Gate Leakage Current
Vds = 0V, Vgs = -4.5V
µA -27 -2
NF Noise Figure[1]
f = 2 GHz
f = 900 MHz
dB 1.4
dB 1.2
G Gain[1]
f = 2 GHz
f = 900 MHz
dB 13.5 14.8 16.5
dB 17.8
OIP3
Output 3rd Order Intercept Point [1,2]
f = 2 GHz
f = 900 MHz
dBm 38.5 41.7
dBm 43
P1dB
Output 1dB Compressed[1]
f = 2 GHz
f = 900 MHz
dBm 28.5 30
dBm
29.6
PAE Power Added Efficiency
f = 2 GHz
f = 900 MHz
% 52 68.9
% 68.6
ACLR
Adjacent Channel Leakage
Power Ratio[1,3]
Offset BW = 5 MHz
Offset BW = 10 MHz
dBc -58.9
dBc -62.7
Notes:
1. Measurements obtained using production test board described in Figure 6 and PAE tested at P1dB condition.
2. I ) 2 GHz OIP3 test condition: F1 = 2.0 GHz, F2 = 2.01 GHz and Pin = -5 dBm per tone.
II ) 900 MHz OIP3 test condition: F1 = 900 MHz, F2 = 910 MHz and Pin = -5 dBm per tone.
3. ACLR test spec is based on 3GPP TS 25.141 V5.3.1 (2002-06)
- Test Model 1
- Active Channels: PCCPCH + SCH + CPICH + PICH + SCCPCH + 64 DPCH (SF=128)
- Freq = 2140 MHz
- Pin = -5 dBm
- Channel Integrate Bandwidth = 3.84 MHz
4. Use proper bias, board, heatsink and derating designs to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and
application note for more details.
Input
50 Ohm
Transmission
Line and
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
Γ_mag = 0.69
Γ_ang = -164°
(1.1 dB loss)
Output
Matching Circuit
DUT Γ_mag = 0.65
Γ_ang = -163°
(0.9 dB loss)
50 Ohm
Transmission
Line and
Drain Bias T
(0.3 dB loss)
Output
Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE and ACLR measurements. This circuit achieves a
trade-off between optimal OIP3, P1dB and VSWR. Circuit losses have been de-embedded from actual measurements.
3



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RF Input
1.8 nH
1.2 pF
50 Ohm
.02 λ
110 Ohm
.03 λ
15 nH
15 Ohm
DUT
2.2 µF
Gate
DC Supply
110 Ohm 50 Ohm
.03 λ .02 λ
2.7 nH
1.2 pF
47 nH
2.2 µF
Drain
DC Supply
RF Output
Figure 7. Simplified schematic of production test board. Primary purpose is to show 15 Ohm series resistor placement in
gate supply. Transmission line tapers, tee intersections, bias lines and parasitic values are not shown.
Gamma Load and Source at Optimum OIP3 and P1dB Tuning Conditions
The device’s optimum OIP3 and P1dB measurements were determined using a load pull system at 4.5V,
200 mA quiesent bias:
Optimum OIP3
Freq
(GHz)
Gamma Source
Mag Ang
0.9
0.776
152
2.0
0.872
-171
2.4
0.893
-162
3.9
0.765
-132
Gamma Load
Mag Ang
0.549
0.683
0.715
0.574
-178
-179
-174
-144
OIP3
(dBm)
43.3
43.1
42.8
41.7
Gain
(dB)
17.94
15.06
14.03
9.47
P1dB
(dBm)
29.63
30.12
29.90
29.02
PAE
(%)
63.8
66.8
64.5
52
Optimum P1dB
Freq
(GHz)
Gamma Source
Mag Ang
0.9
0.773
153
2.0
0.691
147
2.4
0.797
164
3.9
0.602
-163
Gamma Load
Mag Ang
0.784
0.841
0.827
0.794
-173
-166
-166
-155
OIP3
(dBm)
38.0
36.4
36.2
35.4
Gain
(dB)
19.28
10.34
8.43
7.03
P1dB
(dBm)
31.9
31.4
31.2
31
PAE
(%)
54.23
38.15
37.38
32.72
4



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