ATF-501P8 Datasheet PDF - AVAGO

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ATF-501P8
AVAGO

Part Number ATF-501P8
Description High Linearity Enhancement Mode Pseudomorphic HEMT
Page 22 Pages


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ATF-501P8
High Linearity Enhancement Mode[1]
Pseudomorphic HEMT in 2x2 mm2 LPCC[3] Package
Data Sheet
Description
Avago Technologies’s ATF-501P8 is a single-voltage
high linearity, low noise E-pHEMT housed in an 8-
lead JEDEC-standard leadless plastic chip carrier
(LPCC[3]) package. The device is ideal as a medium-
power amplifier. Its operating frequency range is from
400 MHz to 3.9 GHz.
The thermally efficient package measures only 2mm
x 2mm x 0.75mm. Its backside metalization provides
excellent thermal dissipation as well as visual
evidence of solder reflow. The device has a Point
MTTF of over 300 years at a mounting temperature
of +85ºC. All devices are 100% RF & DC tested.
Notes:
1. Enhancement mode technology employs a single positive Vgs, eliminating
the need of negative gate voltage associated with conventional depletion
mode devices.
2. Refer to reliability datasheet for detailed MTTF data.
3. Conforms to JEDEC reference outline MO229 for DRP-N.
4. Linearity Figure of Merit (LFOM) is essentially OIP3 divided by DC bias power.
Features
Single voltage operation
High Linearity and P1dB
Low Noise Figure
Excellent uniformity in product specifications
Small package size: 2.0 x 2.0 x 0.75 mm3
Point MTTF > 300 years[2]
MSL-1 and lead-free
Tape-and-Reel packaging option available
Specifications
2 GHz; 4.5V, 280 mA (Typ.)
45.5 dBm Output IP3
29 dBm Output Power at 1dB gain compression
1 dB Noise Figure
15 dB Gain
14.5 dB LFOM[4]
65% PAE
23oC/W thermal resistance
Pin Connections and Package Marking
Pin 8
Pin 7 (Drain)
Pin 6
Pin 5
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Bottom View
Pin 1 (Source)
Pin 8
Pin 2 (Gate)
Pin 3
0Px
Pin 7 (Drain)
Pin 6
Pin 4 (Source)
Pin 5
Top View
Note:
Package marking provides orientation and identification:
0P= Device Code
x= Date code indicates the month of manufacture.
Applications
Front-end LNA Q2 and Q3, Driver or Pre-driver Amplifier
for Cellular/PCS and WCDMA wireless infrastructure
Driver Amplifier for WLAN, WLL/RLL and MMDS
applications
General purpose discrete E-pHEMT for other high linearity
applications
Attention:
Observe precautions for
handling electrostatic
sensitive devices.
ESD Machine Model (Class A)
ESD Human Body Model (Class 1C)
Refer to Agilent Application Note A004R:
Electrostatic Discharge Damage and Control.



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ATF-501P8 Absolute Maximum Ratings[1]
Symbol
VDS
VGS
VGD
IDS
IGS
Pdiss
Pin max.
TCH
TSTG
θch_b
Parameter
DrainSource Voltage[2]
GateSource Voltage[2]
Gate Drain Voltage[2]
Drain Current[2]
Gate Current
Total Power Dissipation[3]
RF Input Power
Channel Temperature
Storage Temperature
Thermal Resistance[4]
Units
V
V
V
A
mA
W
dBm
°C
°C
°C/W
Absolute
Maximum
7
-5 to 0.8
-5 to 1
1
12
3.5
30
150
-65 to 150
23
Notes:
1. Operation of this device in excess of any one
of these parameters may cause permanent
damage.
2. Assumes DC quiescent conditions.
3. Board (package belly) temperatureTB is 25°C.
Derate 43.5 mW/°C for TB > 69.5°C.
4. Channel-to-board thermal resistance
measured using 150°C Liquid Crystal
Measurement method.
800
Vgs=0.7V
700
600 Vgs=0.65V
500
Vgs=0.6V
400
300 Vgs=0.55V
200 Vgs=0.5V
100
0
01 2 3 4 5
Vds (V)
Figure 1. Typical IV curve
(Vgs = 0.01V) per step.
6
100
Cpk=1.61
Stdev=0.33
80
60
3 Std
40
+3 Std
20
0
13 14
Figure 4. Gain.
15
GAIN (dB)
16
17
Product Consistency Distribution Charts at 2 GHz, 4.5V, 200 mA[5,6]
120
Cpk=1.76
100 Stdev=0.3
120
Cpk=1.51
100 Stdev=3.38
80
–3 Std
60
+3 Std
80
3 Std
60
+3 Std
40 40
20 20
0
27.5 28 28.5 29 29.5 30 30.5
P1dB (dBm)
Figure 2. P1dB.
0
45 55
Figure 3. PAE.
65
PAE (%)
75
85
100
Cpk=1.1
Stdev=0.87
80
60
3 Std
40
+3 Std
20
0
42 43 44 45 46 47 48 49 50
OIP3 (dBm)
Figure 5. OIP3.
Notes:
5. Distribution data sample size is 300 samples taken from 3 different wafers and 3 different lots.
Future wafers allocated to this product may have nominal values anywhere between the upper and
lower limits.
6. Measurements are made on production test board, which represents a trade-off between optimal
OIP3, P1dB and VSWR. Circuit losses have been de-embedded from actual measurements.
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ATF-501P8 Electrical Specifications
TA = 25°C, DC bias for RF parameters is Vds = 4.5V and Ids = 280 mA unless otherwise specified.
Symbol
Parameter and Test Condition
Units
Min.
Typ.
Max.
Vgs Operational Gate Voltage
Vds = 4.5V, Ids = 280 mA
V
0.42 0.55 0.67
Vth Threshold Voltage
Vds = 4.5V, Ids = 32 mA
V
0.33
Idss Saturated Drain Current
Vds = 4.5V, Vgs = 0V
µA 5
Gm Transconductance
Vds = 4.5V, Gm = Ids/Vgs;
Vgs = Vgs1 Vgs2
Vgs1 = 0.55V, Vgs2 = 0.5V
mmho
1872
Igss Gate Leakage Current
Vds = 0V, Vgs = -4.5V
µA -30 -0.8
NF Noise Figure[1]
f = 2 GHz
f = 900 MHz
dB 1
dB — — —
G Gain[1]
f = 2 GHz
f = 900 MHz
dB
13.5 15
16.5
dB 16.6
OIP3
Output 3rd Order Intercept Point[1,2]
f = 2 GHz
f = 900 MHz
dBm 43
dBm
45.5
42
P1dB
Output 1dB Compressed[1]
f = 2 GHz
f = 900 MHz
dBm 27.5 29
dBm
27.3
PAE Power Added Efficiency[1]
f = 2 GHz
f = 900 MHz
% 50 65
% 49
ACLR
Adjacent Channel Leakage
Power Ratio[1,3]
Offset BW = 5 MHz
Offset BW = 10 MHz
dBc 63.9
dBc 64.1
Notes:
1. Measurements at 2 GHz obtained using production test board described in Figure 2 while measurement at 0.9GHz obtained from load pull tuner.
2. i ) 2 GHz OIP3 test condition: F1 = 2.0 GHz, F2 = 2.01 GHz and Pin = -5 dBm per tone.
ii ) 900 MHz OIP3 test condition: F1 = 900 MHz, F2 = 910 MHz and Pin = -5dBm per tone.
3. ACLR test spec is based on 3GPP TS 25.141 V5.3.1 (2002-06)
- Test Model 1
- Active Channels: PCCPCH + SCH + CPICH + PICH + SCCPCH + 64 DPCH (SF=128)
- Freq = 2140 MHz
- Pin = -5 dBm
- Channel Integrate Bandwidth = 3.84 MHz
4. Use proper bias, board, heatsinking and derating designs to ensure max channel temperature is not exceeded.
See absolute max ratings and application note for more details.
Input
50 Ohm
Transmission
Line and
Drain Bias T
(0.3 dB loss)
Input
Matching
Circuit
Γ_mag=0.79
Γ_ang=-164°
(1.1 dB loss)
DUT
Output
Matching
Circuit
Γ_mag=0.69
Γ_ang=-163°
(0.9 dB loss)
50 Ohm
Transmission
Line and
Drain Bias T
(0.3 dB loss)
Output
Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE measurements at 2 GHz. This circuit achieves a
trade-off between optimal OIP3, P1dB and VSWR. Circuit losses have been de-embedded from actual measurements.
3



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RF Input
1.8 nH
1.2 pF
50 Ohm
.02
110 Ohm
.03
15 nH
15 Ohm
DUT
110 Ohm
.03
50 Ohm
.02
2.2 µF
1.2 pF
47 nH
3.3 nH
RF Output
2.2 µF
Gate
Supply
Drain
Supply
Figure 3. Simplified schematic of production test board. Primary purpose is to show 15 Ohm series resistor placement in
gate supply. Transmission line tapers, tee intersections, bias lines and parasitic values are not shown.
Gamma Load and Source at Optimum OIP3 and P1dB Tuning Conditions
The devices optimum OIP3 and P1dB measurements were determined using a load pull system at 4.5V
280 mA and 4.5V 400 mA quiesent bias respectively:
Typical Gammas at Optimum OIP3 at 4.5V 280 mA
Freq (GHz)
0.9
2.0
2.4
3.9
Optimized for maximum OIP3 at 4.5V 280 mA
OIP3 Gain P1dB
46.42
45.50
44.83
43.97
16.03
15.07
12.97
6.11
26.67
28.93
29.03
27.33
PAE
45.80
50.30
45.70
33.90
Gamma Source
0.305 < -140
0.806 < -179.2
0.756 < -167
0.782 < -162
Gamma Load
0.577 < 162
0.511 < 164
0.589 < -168
0.524 < -153
Typical Gammas at Optimum P1dB at 4.5V 280mA
Freq (GHz)
0.9
2.0
2.4
3.9
Optimized for maximum P1dB at 4.5V 280 mA
OIP3 Gain P1dB
39.29
41.79
42.37
42.00
20.90
14.72
11.25
5.63
30.49
30.60
30.24
28.26
PAE
41.00
45.30
39.70
25.80
Gamma Source
0.859 < 165
0.76 < -171
0.745 < -166
0.759 < -159
Gamma Load
0.757 < 179
0.691 < -168
0.694 < -161
0.708 < -149
Typical Gammas at Optimum OIP3 at 4.5V 400 mA
Freq (GHz)
0.9
2.0
2.4
3.9
Optimized for maximum OIP3 at 4.5V 400 mA
OIP3 Gain P1dB
49.15
48.18
47.54
45.44
16.85
14.72
12.47
8.05
27.86
29.36
29.10
28.49
PAE
44.20
48.89
46.83
37.02
Gamma Source
0.5852 < -135.80
0.7267 < -175.37
0.6155 < -171.71
0.7888 < -148.43
Gamma Load
0.4785 < 177.00
0.7338 < 179.56
0.5411 < -172.02
0.5247 < -145.84
Typical Gammas at Optimum P1dB at 4.5V 400 mA
Freq (GHz)
0.9
2.0
2.4
3.9
Optimized for maximum P1dB at 4.5V 400 mA
OIP3 Gain P1dB
41.78
21.84
31.23
43.28
14.83
31.03
42.46
11.90
30.66
42.94
7.70
29.56
PAE
49.97
44.78
41.00
33.06
Gamma Source
0.7765 < 168.50
0.8172 < -175.74
0.8149 < -163.78
0.8394 < -151.21
Gamma Load
0.7589 < -175.09
0.8011 < -165.75
0.8042 < -161.79
0.7826 < -149.00
4



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