ATF-331M4 Datasheet PDF - AVAGO


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ATF-331M4
AVAGO

Part Number ATF-331M4
Description Low Noise Pseudomorphic HEMT
Page 14 Pages

ATF-331M4 datasheet pdf
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ATF-331M4
Low Noise Pseudomorphic HEMT
in a Miniature Leadless Package
Data Sheet
Description
Avago Technologies’s ATF-331M4 is a high linearity, low
noise pHEMT housed in a miniature leadless package.
The ATF-331M4’s small size and low profile makes it
ideal for the design of hybrid modules and other space-
constraint devices.
Based on its featured performance, ATF-331M4 is ideal for
the first or second stage of base station LNA due to the
excellent combination of low noise figure and enhanced
linearity[1]. The device is also suitable for applications
in Wireless LAN, WLL/RLL, MMDS, and other systems
requiring super low noise figure with good intercept in
the 450 MHz to 10 GHz frequency range.
Note:
1. From the same PHEMT FET family, the smaller geometry ATF-34143
may also be considered for the higher gain performance, particularly
in the higher frequency band (1.8 GHz and up).
MiniPak 1.4 mm x 1.2 mm Package
Px
Features
Low noise figure
Excellent uniformity in product specifications
1600 micron gate width
Miniature leadless package 1.4 mm x 1.2 mm x 0.7 mm
Tape-and-reel packaging option available
Specifications
2 GHz; 4 V, 60 mA (Typ.)
0.6 dB noise figure
15 dB associated gain
19 dBm output power at 1 dB gain compression
31 dBm output 3rd order intercept
Applications
Tower mounted amplifier, low noise amplifier and
driver amplifier for GSM/TDMA/CDMA base stations
LNA for WLAN, WLL/RLL, MMDS and wireless data
infrastructures
General purpose discrete PHEMT for other ultra low
noise applications
Pin Connections and Package Marking
Source
Drain
PxPin 3 Pin 4
Gate Source
Pin 2 Pin 1
Note:
Top View. Package marking provides orientation, product identification
and date code.
“P” = Device Type Code
“x” = Date code character. A different character is assigned for each
month and year.



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ATF-331M4 Absolute Maximum Ratings[1]
Symbol
VDS
VGS
VGD
IDS
Pdiss
Pin max.
TCH
TSTG
jc
Parameter
Drain-Source Voltage [2]
Gate-Source Voltage [2]
Gate Drain Voltage [2]
Drain Current [2]
Total Power Dissipation [4]
RF Input Power
Channel Temperature [5]
Storage Temperature
Thermal Resistance [6]
Units
V
V
V
mA
mW
dBm
°C
°C
°C/W
Absolute
Maximum
5.5
-5
-5
Idiss[3]
400
20
160
-65 to 160
200
Notes:
1. Operation of this device above any one of
these parameters may cause permanent
damage.
2. Assumes DC quiescent conditions.
3. VGS = 0 V
4. Source lead temperature is 25°C. Derate
5 mW/°C for TL > 40°C.
5. Please refer to failure rates in reliability
data sheet to assess the reliability impact
of running devices above a channel
temperature of 140°C.
6. Thermal resistance measured using 150°C
Liquid Crystal Measurement method.
500
+0.6 V
400
300
0V
200
100 -0.6 V
0
02 46
VDS (V)
Figure 1. Typical Pulsed I-V Curves[7].
(VGS = -0.2 V per step)
8
Note:
7. Under large signal conditions, VGS may
swing positive and the drain current may
exceed Idss.These conditions are acceptable
as long as the Maximum Pdiss and Pin max
ratings are not exceeded.
Product Consistency Distribution Charts[8, 9]
100
80
60
-3 Std
40
20
Cpk = 1.05
Stdev = 0.07
+3 Std
150
120
90
-3 Std
60
30
Cpk = 1.00
Stdev = 1.07
+3 Std
120
100
80
60
40
20
Cpk = 4.37
Stdev = 1.11
-3 Std +3 Std
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
NF (dBm)
Figure 2. NF @ 2 GHz, 4 V, 60 mA.
LSL = 28.5, Nominal = 0.6, USL = 0.8.
0
28
30 32
OIP3 (dBm)
34
36
Figure 3. OIP3 @ 2 GHz, 4 V, 60 mA.
LSL = 28.5, Nominal = 31.0, USL = 36.0
0
13
14 15
GAIN (dB)
16
17
Figure 4. Gain @ 2 GHz, 4 V, 60 mA.
LSL = 13.5, Nominal = 15.0, USL = 16.5
Notes:
8. Distribution data sample size is 349 samples from 4 different wafers. Future wafers allocated to this product may have nominal values anywhere
within the upper and lower spec limits.
9. Measurements made on production test board. This circuit represents a trade-off between an optimal noise match and a realizeable match based
on production test requirements. Circuit losses have been de-embedded from actual measurements.
2



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ATF-331M4 DC Electrical Specifications
TA = 25°C, RF parameters measured in a test circuit for a typical device
Symbol Parameter and Test Condition
Idss[1] Saturated Drain Current
Vds = 1.5 V, Vgs = 0V
Vp[1]
Pinch-off Voltage
Vds = 1.5 V, Ids = 10% of Idss
Id Quiescent Bias Current
Vgs = -0.51 V, Vds = 4 V
Gm[1] ] Transconductance
Vds = 1.5 V, Gm = Idss/Vp
Igdo Gate to Drain Leakage Current
Vgd = -5 V
Igss Gate Leakage Current
Vgd = Vgs = -4V
NF Noise Figure
f = 2 GHz Vds = 4 V, Ids = 60 mA
f = 900 MHz Vds = 4 V, Ids = 60 mA
Ga Associated Gain
f = 2 GHz Vds = 4 V, Ids = 60 mA
f = 900 MHz Vds = 4 V, Ids = 60 mA
OIP3
Output 3rd Order
Intercept Point [3]
f = 2 GHz,
5 dBm Pout/Tone
f = 900 MHz,
5 dBm Pout/Tone
Vds = 4 V, Ids = 60 mA
Vds = 4 V, Ids = 60 mA
P1dB
1dB Compressed
Output Power [3]
f = 2 GHz Vds = 4 V, Ids = 60 mA
f = 900 MHz Vds = 4 V, Ids = 60 mA
Notes:
1. Guaranteed at wafer probe level
2. Typical values are determined from a sample size of 349 parts from 4 wafers.
3. Measurements obtained using production test board described in Figure 5.
Units
mA
V
mA
mmho
A
A
dB
dB
dB
dB
dBm
dBm
dBm
dBm
Min.
175
-0.65
360
13.5
28.5
Typ.[2]
237
-0.5
60
440
42
0.6
0.5
15
21
31
30.8
Max.
305
-0.35
1000
600
0.8
16.5
19 —
18 —
Input
50Ω Input
Transmission Line
Including
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
Γ_mag = 0.13
Γ_ang = 113°
(0.3 dB loss)
50Ω Output
Output
Transmission Line
DUT Including
Gate Bias T
(0.5 dB loss)
Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Associated Gain, P1dB, and OIP3 measurements.
This circuit represents a trade-off between an optimal noise match and a realizable match based on production test requirements.
Circuit losses have been de-embedded from actual measurements.
3



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ATF-331M4 Typical Performance Curves
40
2V
3V
4V
30
40
30
2V
3V
4V
20 20
10 10
0
0 20 40 60 80 100
Ids (mA)
Figure 6. OIP3, IIP3 & Bias[1] at 2 GHz.
0
0 20 40 60 80 100
Ids (mA)
Figure 7. OIP3, IIP3 & Bias[1] at 900 MHz.
25
2V
3V
4V
20
15
10
5
0
0 20 40 60 80
Idsq (mA)
Figure 8. P1dB vs. Bias[1,2] 2 GHz.
100
25
2V
3V
4V
20
15
10
5
0
0 20 40 60 80
Idsq (mA)
Figure 9. P1dB vs. Bias[1] 900 MHz.
100
16
2V
3V
15 4V
1.4
1.2
14 1.0
13 0.8
12 0.6
11 0.4
10 0.2
0 20 40 60 80 100
Id (mA)
Figure 10. NF & Gain vs. Bias[1] at 2 GHz.
22
2V
3V
21 4V
1.4
1.2
20 1.0
19 0.8
18 0.6
17 0.4
16 0.2
0 20 40 60 80 100 120
Id (mA)
Figure 11. NF & Gain vs. Bias[1] at 900 MHz.
Notes:
1. Measurements made on fixed tuned
production test board that was tuned
for optimal gain match with reasonable
noise figure at 4V 60  mA bias. This circuit
represents a trade-off between an optimal
noise match, maximum gain match and
a realizable match based on production
test board requirements. Circuit losses
have been de-embedded from actual
measurements.
2. Quiescent drain current, Idsq, is set
with zero RF drive applied. As P1dB is
approached, the drain current may increase
or decrease depending on frequency and
dc bias point. At lower values of Idsq the
device is running closer to class B as power
output approaches P1dB. This results in
higher P1dB and higher PAE (power added
efficiency) when compared to a device that
is driven by a constant current source as is
typically done with active biasing.
4




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