4. Analog Front End (AFE)
The AFE includes all circuits which are connected directly to the coil terminals. The AFE generates the IC power supply and
handles bi-directional data communication with the reader. The AFE consists of the following blocks:
● Rectifier to generate a DC supply voltage from the AC coil voltage
● Clock extractor
● Switchable load between Coil 1 and Coil 2 for data transmission from tag to the reader
● Field-gap detector for data transmission from the base station to the tag
● ESD protection circuitry
4.1 Data Rate Generator
The data rate of the Atmel ATA5575M2 is programmable to operate at RF/50 (FDX-A mode) and RF/32 (FDX-B mode).
4.2 Write Decoder
The write decoder detects the write gaps and verifies the validity of the data stream according to the Atmel® downlink
protocol (pulse-interval encoding).
4.3 HV Generator
This on-chip charge pump circuit generates the high voltage required for programming the EEPROM.
4.4 DC Supply
Power is supplied externally to the IDIC via the two coil connections. The IC rectifies and regulates this RF source and uses
it to generate its supply voltage.
4.5 Power-On Reset (POR)
The power-on reset circuit blocks the voltage supply to the IDIC until an acceptable voltage threshold has been reached.
This, in turn, triggers the default initialization delay sequence. During this configuration period of 98 field clocks, the
ATA5575M2 is initialized with the configuration data stored in EEPROM byte 16.
4.6 Clock Extraction
The clock extraction circuit uses the external RF signal as its internal clock source.
The control logic module executes the following functions:
● Load mode register with configuration data from EEPROM byte 16 after power-on and during reading
● Controls each EEPROM memory read/write access and handles data protection
● Handle downlink command decoding, detecting protocol violations and error conditions