AT52BC3221A Datasheet PDF - ATMEL Corporation


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AT52BC3221A
ATMEL Corporation

Part Number AT52BC3221A
Description 32-Mbit Flash 8-Mbit PSRAM Stack Memory
Page 30 Pages

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Features
32-Mbit Flash and 4-Mbit/8-Mbit PSRAM
Single 66-ball (8 mm x 10 mm x 1.2 mm) CBGA Package
2.7V to 3.3V Operating Voltage
Flash
32-megabit (2M x 16)
2.7V to 3.3V Read/Write
Access Time – 70 ns
Sector Erase Architecture
– Sixty-three 32K Word Sectors with Individual Write Lockout
– Eight 4K Word Sectors with Individual Write Lockout
Fast Word Program Time – 15 µs
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 12 mA Active
– 13 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Minimum 100,000 Erase Cycles
PSRAM
8-megabit (512K x 16)
2.7V to 3.3V VCC
70 ns Access Time
Extended Temperature Range
ISB0 < 10 µA when Deep Power-Down
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32-Mbit Flash +
8-Mbit PSRAM
Stack Memory
AT52BC3221A
AT52BC3221AT
Preliminary
Device Number
AT52BC3221A
AT52BC3221AT
Flash Boot
Location
Bottom
Top
Flash Plane
Configuration
32M (2M x 16)
32M (2M x 16)
PSRAM
Configuration
8M (512K x 16)
8M (512K x 16)
Rev. 3466A–STKD–11/04
1



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Pin Configuration
CBGA (Top View)
Pin Name
A0 - A18, A19 - A20
CE
OE
WE
RESET
RDY/BUSY
VPP
VCC
GND
I/O0 - I/O15
NC
PLB
PUB
PVCC
PGND
PCS1
ZZ
PWE
POE
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Function
Common Address Input for 8M PSRAM/Flash, Flash Address Input
Flash Chip Enable
Flash Output Enable
Flash Write Enable
Flash Reset
Flash READY/BUSY Output
Flash Power Supply for Accelerated Program/Erase Operations
Flash Power
Flash Ground
Data Inputs/Outputs
No Connect
PSRAM Lower Byte
PSRAM Upper Byte
PSRAM Power
PSRAM Ground
PSRAM Chip Select 1
Low Power Modes
PSRAM Write Enable
PSRAM Output Enable
1 2 3 4 5 6 7 8 9 10 11 12
A
NC NC A20 A11 A15 A14 A13 A12 GND NC NC NC
B
A16 A8 A10 A9 I/O15 PWE I/O14 I/O7
C
WE RDY/BUSY
I/O13 I/O6 I/O4 I/O5
D
PGND RESET
I/O12 ZZ PVCC VCC
E
NC VPP A19 I/O11
I/O10 I/O2 I/O3
F
PLB PUB POE
I/O9 I/O8 I/O0 I/O1
G
A18 A17 A7 A6 A3 A2 A1 PCS1
H
NC NC NC A5 A4 A0 CE GND OE NC NC NC
2 AT52BC3221A(T)
3466A–STKD–11/04



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Block Diagram
AT52BC3221A(T)
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OE WE
ADDRESS
POE PWE
RESET
CE
RDY/BUSY
32-Mbit
FLASH
4/8-Mbit
PSRAM
PCS1
ZZ
DATA
Description
The AT52BC3221A(T) combines a 32-megabit Flash (2M x 16) and an 8-megabit PSRAM
(organized as 512K x 16) in a stacked 66-ball CBGA package. The stacked modules operate
at 2.7V to 3.3V in the extended temperature range.
Absolute Maximum Ratings
Temperature under Bias................................... -25°C to +85°C
Storage Temperature ..................................... -55°C to +150°C
All Input Voltages
except VPP (including NC Pins)
with Respect to Ground ..............................-0.2V to VCC +0.3V
Voltage on VPP
with Respect to Ground ..................................-0.2V to + 6.25V
All Output Voltages
with Respect to Ground ..............................-0.2V to VCC +0.3V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC and AC Operating Range
Operating Temperature (Case)
VCC Power Supply
-25°C - 85°C
2.7V to 3.3V
3466A–STKD–11/04
3



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32-megabit
Flash Memory
Description
Block Diagram
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The 32-megabit Flash is a a 2.7-volt memory organized as 2,097,152 words of 16 bits each.
The memory is divided into 71 sectors for erase operations. The device has CE and OE con-
trol signals to avoid any bus contention. This device can be read or reprogrammed using a
single power supply, making it ideally suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector (see “Sector Lockdown” section).
To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend
feature. This feature will put the erase or program on hold for any amount of time and let the
user read data from or program data to any of the remaining sectors within the memory. The
end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by
the toggle bit.
The VPP pin provides data protection. When the VPP input is below 0.4V, the program and
erase functions are inhibited. When VPP is at 0.9V or above, normal program and erase opera-
tions can be performed.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement
of entering the three-byte program sequence is offered to further improve programming time.
After entering the six-byte code, only single pulses on the write control lines are required for
writing into the device. This mode (Single Pulse Word Program) is exited by powering down
the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back
to VCC. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not
work while in this mode; if entered they will result in data being programmed into the device. It
is not recommended that the six-byte code reside in the software of the final product but only
exist in external programming code.
I/O0 - I/O15
OUTPUT
BUFFER
INPUT
BUFFER
A0 - A20
INPUT
BUFFER
ADDRESS
LATCH
Y-DECODER
X-DECODER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
Y-GATING
MAIN
MEMORY
COMMAND
REGISTER
WRITE STATE
MACHINE
CE
WE
OE
RESET
PROGRAM/ERASE
VOLTAGE SWITCH
RDY/BUSY
VPP
VCC
GND
4 AT52BC3221A(T)
3466A–STKD–11/04




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