AT-31011 Datasheet PDF - AVAGO

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AT-31011
AVAGO

Part Number AT-31011
Description High Performance NPN Silicon Bipolar Transistor
Page 10 Pages


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AT-31011, AT-31033
Low Current, High Performance NPN 
Silicon Bipolar Transistor
Data Sheet
Description
Avago’s AT-31011 and AT-31033 are high performance
NPN bipolar transistors that have been optimized for op-
eration at low voltages, making them ideal for use in bat-
tery powered applications in wireless markets. The AT-
31033 uses the 3 lead SOT‑23, while the AT-31011 places
the same die in the higher performance 4 lead SOT‑143.
Both packages are industry standards compatible with
high volume surface mount assembly techniques.
The 3.2 micron emitter-to-emitter pitch and reduced
parasitic design of these transistors yields extremely high
performance products that can perform a mul­tiplicity
of tasks. The 10 emitter finger interdigitated geometry
yields an extremely fast transistor with low operating
currents and reasonable impedances.
Optimized performance at 2.7 V makes these devices
ideal for use in 900 MHz, 1.9 GHz, and 2.4 GHz battery
operated systems as an LNA, gain stage, buffer, oscil­la­
tor, or active mixer. Applica­tions include cellular and PCS
handsets as well as Industrial-Scientific-Medical systems.
Typical amplifier designs at 900 MHz yield 1.3 dB noise
figures with 11 dB or more associated gain at a 2.7 V, 1
mA bias. Moderate output power capability (+9 dBm
P1dB) coupled with an excellent noise figure yields high
dynamic range for a microcurrent device. High gain ca-
pability at 1 V, 1 mA makes these devices a good fit for 900
MHz pager appli­ca­tions.
The AT-3 series bipolar transistors are fabricated using
an optimized version of Avago’s 10 GHz fT, 30 GHz fmax
Self-Aligned-Transistor (SAT) process. The die are nitride
passivated for surface protection. Excellent device uni-
formity, performance and reliability are produced by the
use of ion-implantation, self-alignment techniques, and
gold metalization in the fabrication of these devices.
Features
High Performance Bipolar Transistor Optimized for
Low Current, Low Voltage Operation
900 MHz Performance:
AT-31011: 0.9 dB NF, 13 dB GA
AT-31033: 0.9 dB NF, 11 dB GA
Characterized for End-Of-Life Battery Use (2.7 V)
SOT-143 SMT Plastic Package
Tape-And-Reel Packaging Option Available
Lead-free
Pin Connections and Package Marking
EMITTER COLLECTOR
310x
BASE EMITTER
SOT-143 (AT-31011)
COLLECTOR
310x
BASE EMITTER
SOT-23 (AT-31033)
Notes:
Top View. Package Marking provides orientation and identification.
"x" is the date code.



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AT-31011, AT-31033 Absolute Maximum Ratings
Symbol     Parameter
Units   Absolute Maximum[1]
VEBO
VCBO
VCEO
IC
PT
Tj
TSTG
Emitter-Base Voltage
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Power Dissipation[2,3]
Junction Temperature
Storage Temperature
V
V
V
mA
mW
°C
°C
1.5
11
5.5
16
150
150
-65 to 150
Notes:
1. Operation of this device above any one of these parameters may cause permanent damage.
2. Tmounting surface = 25°C.
3. Derate at 1.82 mW/°C for TC > 67.5°C.
Thermal Resistance[2]:
     θjc = 550°C/W
Electrical Specifications, TA = 25°C
AT-31011 AT-31033
Symbol    Parameters and Test Conditions Units Min Typ Max Min Typ  Max
NF
GA
hFE
ICBO
IEBO
Noise Figure
VCE = 2.7 V, IC = 1 mA
Associated Gain
VCE = 2.7 V, IC = 1 mA
Forward Current
Transfer Ratio
Collector Cutoff Current
Emitter Cutoff Current
f = 0.9 GHz dB
0.9[1] 1.2[1]
0.9[2] 1.2[2]
f = 0.9 GHz
VCE = 2.7 V
IC = 1 mA
VCB = 3 V
VEB = 1 V
dB 11[1] 13[1]
9[2] 11[2]
- 70 300 70 300
µA
µA
0.05
0.1
0.2
1.5
0.05
0.1
0.2
1.5
Notes:
1. Test circuit B, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.4 dB; output loss = 0.4 dB.
2. Test circuit A, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.4 dB; output loss = 0.4 dB.
VBB
1000 pF
W = 10 L = 1860
W = 10 L = 1000
W = 30 L = 100
TEST CIRCUIT
BOARD MATL = 0.062" FR-4 (ε = 4.8)
DIMENSIONS IN MILS
VCC
W = 10 L = 1860
25
1000 pF
W = 30 L = 100
W = 10 L = 1025
TEST CIRCUIT A: W = 20 L = 100
TEST CIRCUIT B: W = 20 L = 200 x 2
NOT TO SCALE
Figure 1. Test Circuit for Noise Figure and Associated Gain. This Circuit is a Compromise Match Between Best Noise Fig-
ure, Best Gain, Stability, a Practical, Synthesizable Match, and a Circuit Capable of Matching Both the AT-305 and AT-310
Geometries.
AT-31011 fig 1




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Characterization Information, TA = 25°C
Symbol Parameters and Test Conditions Units
P1dB
G1dB
IP3
|S21|E2
CCB
Power at 1 dB Gain Compression (opt tuning)
VCE = 2.7 V, IC = 10 mA
Gain at 1 dB Gain Compression (opt tuning)
VCE = 2.7 V, IC = 10 mA
Output Third Order Intercept Point,
VCE = 2.7 V, IC = 10 mA (opt tuning)
Gain in 50 Ω System; VCE = 2.7 V, IC = 1 mA
Collector-Base Capacitance
f = 0.9 GHz dBm
f = 0.9 GHz dB
f = 0.9 GHz
f = 0.9 GHz
VCB = 3V, f = 1 MHz
dBm
dB
pF
AT-31011
Typ
9
15
20
10
0.04
AT-31033
Typ
9
13
20
9
0.04
2.5
AMPLIFIER NF
2
1.5
1 NF MIN.
0.5
1 mA
10 mA
00 0.5 1 1.5 2
FREQUENCY (GHz)
2.5
Figure 2. AT-31011 and AT-31033 Minimum Noise
Figure and Amplifier NF[1] vs. Frequency and Current
at Vce = 2.7 V.
AT-31011 fig 2
25
20
10 mA
15
1 mA
10
5
00 0.5 1.0 1.5 2.0 2.5
FREQUENCY (GHz)
Figure 3. AT-31011 Associated Gain at Optimum Noise
Match vs. Frequency and Current at Vce = 2.7 V.
AT-31011 fig 3
25
20
10 mA
15
10
1 mA
5
00 0.5 1.0 1.5 2.0 2.5
FREQUENCY (GHz)
Figure 4. AT-31033 Associated Gain at Optimum Noise
Match vs. Frequency and Current at Vce = 2.7 V.
AT-31011 fig 4
10
10 mA
8
5 mA
6
4
2 mA
2
2 mA
5 mA
10 mA
00 0.5 1.0 1.5 2.0 2.5
FREQUENCY (GHz)
20
16
12
8
2 mA
4 5 mA
10 mA
00 0.5 1.0 1.5 2.0 2.5
FREQUENCY (GHz)
16
12
8
4
2 mA
5 mA
10 mA
00 0.5 1.0 1.5 2.0 2.5
FREQUENCY (GHz)
Figure 5. AT-31011 and AT-31033 Power at 1 dB Gain
Compression vs. Frequency and Current at Vce = 2.7 V.
AT-31011 fig 5
Figure 6. AT-31011 1 dB Compressed Gain vs. Frequen-
cy and Current at Vce = 2.7 V.
AT-31011 fig 6
Figure 7. AT-31033 1 dB Compressed Gain vs. Frequen-
cy and Current at Vce = 2.7 V.
AT-31011 fig 7
Note:
1. Amplifier NF represents the noise figure which can be expected in a real circuit representing reasonable reflection coefficients and including
circuit losses.




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AT-31011, AT-31033 Typical Performance
15 20
12
10 mA
9 5 mA
16
12
6
2 mA
3
2 mA
5 mA
10 mA
00 0.5 1.0 1.5 2.0 2.5
FREQUENCY (GHz)
Figure 8. AT-31011 and AT-31033 Power at 1 dB Gain
Compression vs. Frequency and Current at Vce = 5 V.
AT-31011 fig 8
8
2 mA
4 5 mA
10 mA
00 0.5 1.0 1.5 2.0 2.5
FREQUENCY (GHz)
Figure 9. AT-31011 1 dB Compressed Gain vs. Frequen-
cy and Current at Vce = 5 V.
AT-31011 fig 9
20
16
12
8
2 mA
4 5 mA
10 mA
00 0.5 1.0 1.5 2.0 2.5
FREQUENCY (GHz)
Figure 10. AT-31033 1 dB Compressed Gain vs. Fre-
quency and Current at Vce = 5 V.
AT-31011 fig 10
4
5 mA
2
0
2 mA
-2
-40 0.5 1.0 1.5 2.0 2.5
FREQUENCY (GHz)
Figure 11. AT-31011 and AT-31033 Power at 1 dB Gain
Compression vs. Frequency and Current at Vce = 1 V.
AT-31011 fig 11
20
16
5 mA
12
2 mA
8
4
00 0.5 1.0 1.5 2.0 2.5
FREQUENCY (GHz)
Figure 12. AT-31011 1 dB Compressed Gain vs. Fre-
quency and Current at Vce = 1 V.
AT-31011 fig 12
20
16
5 mA
12
8
2 mA
4
00 0.5 1.0 1.5 2.0 2.5
FREQUENCY (GHz)
Figure 13. AT-31033 1 dB Compressed Gain vs. Fre-
quency and Current at Vce = 1 V.
AT-31011 fig 13
25
20
Ga
15
10
NF
5
2.5 25
2.0 20
1.5 15
1.0 10
0.5 5
Ga
NF
2.5
2.0
1.5
1.0
0.5
0
IM3 (dBc)
IM5 (dBc)
IM7 (dBc)
-20
-40
-60
0-50 0
50 1000
TEMPERATURE (°C)
Figure 14. AT-31011 Noise Figure and Associated Gain
at Vce = 2.7 V, Ic = 1 mA vs. Temperature in Test Circuit,
Figure 1. (Circuit LoAsTs-e3s1011 fig 14
De-embedded)
0-50 0
50 1000
TEMPERATURE (°C)
Figure 15. AT-31033 Noise Figure and Associated Gain
at Vce = 2.7 V, Ic = 1 mA vs. Temperature in Test Circuit,
Figure 1. (Circuit LoAssTe-s31011 fig 15
De-embedded)
-80-9
-6 -3 0 3
POWER PER TONE (dBm)
6
Figure 16. AT-31011 and AT-31033 Intermodulation
Products vs. Output Power at Vce = 2.7 V, Ic = 10 mA,
900 MHz with OptimATa-l3T1u0n1in1gf.ig 16




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