AS4C1M16S Datasheet PDF - Alliance Memory

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AS4C1M16S
Alliance Memory

Part Number AS4C1M16S
Description 1M x 16 bit Synchronous DRAM
Page 30 Pages


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AS4C1M16S
Alliance Confidential
1M x 16 bit Synchronous DRAM (SDRAM)
Features
Fast access time: 5.4ns
Fast clock rate: 143 MHz
Self refresh mode: standard
Internal pipelined architecture
512K word x 16-bit x 2-bank
Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
Individual byte controlled by LDQM and UDQM
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
JEDEC standard +3.3V±0.3V power supply
Interface: LVTTL
50-pin 400 mil plastic TSOP II package
-Pb and Halogen Free
Overview
The AS4C1M16S SDRAM is a high-speed
CMOS synchronous DRAM containing 16 Mbits. It is
internally configured as a dual 512K word x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Each of the 512K x 16 bit banks is organized
as 2048 rows by 256 columns by 16 bits. Read and
write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue
for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of a BankActivate command which is
then followed by a Read or Write command.
The AS4C1M16S provides for programmable
Read or Write burst lengths of 1, 2, 4, 8, or full page,
with a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use. By having a programmable
mode register, the system can choose the
most suitable modes to maximize its performance.
These devices are well suited for applications
requiring high memory bandwidth and particularly
well suited to high performance PC applications
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Table 1. Key Specifications
AS4C1M16
tCK3 Clock CycSle time(min.)
tRAS Row Active time (min.)
tAC3 Access time from CLK (max.)
tRC
Row Cycle time(min.)
7
7 ns
42 ns
5.4 ns
63 ns
Table 2. Ordering Information
Part Number
Frequency
AS4C1M16S-7TCN 143MHz
T: indicates TSOP II package
N: indicates Pb and Halogen Free
Type
TSOPII
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Figure 1 Pin Assignment (Top View)
AS4C1M16S
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2
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Figure 2. Block Diagram
CLK
CKE
CS#
RAS#
CAS#
WE#
CLOCK
BUFFER
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10/AP
COLUMN
COUNTER
MODE
REGISTER
A0
A9
A11
ADDRESS
BUFFER
REFRESH
COUNTER
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AS4C1M16S
2048x256x16
CELL ARRAY
(BANK #0)
Column Decoder
DQs
Buffer
DQ0
DQ15
LDQM, UDQM
2048x256x16
CELL ARRAY
(BANK #1)
Column Decoder
3
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AS4C1M16S
Pin Descriptions
Symbol
CLK
Type
Input
CKE
Input
A11
A0-A10
Input
Input
CS# Input
RAS#
Input
CAS#
Input
WE#
Input
LDQM,
UDQM
Input
Table 3. Pin Details of EM636165
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If
CKE goes low synchronously with clock (set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state of
output and burst address is frozen as long as the CKE remains low. When both
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device enters
Power Down and Self Refresh modes, where CKE becomes asynchronous until
exiting the same mode. The input buffers, including CLK, are disabled during
Power Down and Self Refresh modes, providing low standby power.
Bank Activate: A11 (BA) defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs: A0-A10 are sampled during the BankActivate command (row
address A0-A10) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 512K available in the
respective bank. During a Precharge command, A10 is sampled to determine if
both banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is
considered part of the command code.http://www.DataSheet4U.net/
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH,"
either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH," the BankActivate command is
selected and the bank designated by BA is turned on to the active state. When the
WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access
is started by asserting CAS# "LOW." Then, the Read or Write command is
selected by asserting WE# "LOW" or "HIGH."
Write Enable: The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK. The
WE# input is used to select the BankActivate or Precharge command and Read or
Write command.
Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent I/O
buffer controls. The I/O buffers are placed in a high-z state when LDQM/UDQM is
sampled HIGH. Input data is masked when LDQM/UDQM is sampled HIGH during
a write cycle. Output data is masked (two-clock latency) when LDQM/UDQM is
sampled HIGH during a read cycle. UDQM masks DQ15-DQ8, and LDQM masks
DQ7-DQ0.
4
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