AR7242 Datasheet PDF - Atheros

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AR7242
Atheros

Part Number AR7242
Description A High Performance And Cost-Effective Network Processor
Page 30 Pages


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Data Sheet
April 2011
AR7242: A High Performance And Cost-Effective Network
Processor
General Description
The Atheros AR7242 is a high performance
and cost effective network processor for access
point, router, and gateway applications. It
includes a MIPS 24Kc processor, PCI Express
1.1 host interface, integrated 10/100 Mbps
Fast Ethernet MAC/PHY, one RGMII port,
one USB 2.0 MAC/PHY, and external memory
interface for serial Flash, DDR1 or DDR2
interface, an I2S audio interface, a high-speed
UART, and GPIOs that can be used for LED
controls or other general purpose interface
configurations.
The AR7242 is a memory-centric architecture
including various DMA controlled interfaces
that access the DDR memory.
The AR7242 network processor, when paired
with the AR928x/AR938x/AR939x single
chip 802.11n MAC/BB/Radio family,
provides the best-in-class WLAN solution
capable of supporting 802.11b/g/n standards.
Features
Integrated MIPS 24 K 32-bit processor
operating at up to 400 MHz
64 K instruction cache and 32 K data cache
Integrated 10/100 802.3 Ethernet LAN port
and one RGMII port
16-bit DDR1 or DDR2 memory interface
supporting up to 400 M transfers per
second
An external serial Flash memory interface
(maximum 16 MBytes)
One USB 2.0 controller with built-in MAC/
PHY
High-speed UART and multiple GPIO pins
for general purpose I/O or LED control
A single lane PCI Express 1.1 interface that
can be used for interfacing to the AR928x/
AR938x/AR939x single chip 802.11n
MAC/BB/Radio
JTAG port support for processor core
14 mm x 14 mm 128-pin LQFP lead-free
package
System Block Diagram
© 2010-2011 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, ETHOS®, IQUE®, No
New Wires®, Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-
Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, ROCm™,
amp™, Install N Go™, Simpli-Fi™, SmartLink™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered
trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
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PRELIMINARY
2 • AR7242 Network Processor
2 April 2011
Atheros Communications, Inc.
COMPANY CONFIDENTIAL



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PRELIMINARY
Table of Contents
General Description ........................................ 1
Features ............................................................ 1
System Block Diagram ................................... 1
1 Pin Descriptions ............................ 9
2 System Architecture .................... 17
2.1 MIPS Processor ....................................... 18
2.2 Configuration ......................................... 18
2.3 AR7242 Address MAP .......................... 19
2.4 AHB Master Bus ..................................... 19
2.5 APB Bridge .............................................. 19
2.6 DDR Memory Controller ...................... 19
2.7 PCIE Root Complex ............................... 21
2.7.1 Overview ..................................... 21
2.7.2 PCIE Root Complex Initialization
Sequence ...................................... 21
2.7.3 Power Management ................... 21
2.7.4 Interrupts ..................................... 21
2.7.5 Error Reporting Capability and
Status Checking .......................... 21
2.8 PLL ........................................................... 22
2.8.1 Basic Clocking ............................. 22
2.8.2 PLL INITIALIZATION
SEQUENCE ................................. 22
2.8.3 400 MHz Setup Procedure ......... 22
2.9 Serial Flash (SPI) .................................... 23
2.10 UART ...................................................... 23
2.11 GE0 and GE1 .......................................... 23
2.12 MDC/MDIO Interface ......................... 23
2.13 Ethernet MAC/PHY Controller ......... 24
2.13.4 VLAN Support ............................ 25
2.13.5 Quality of Service (QoS) For MAC/
PHY Port ...................................... 26
2.14 Rate Limiting ......................................... 26
2.15 Broadcast Storm Control ...................... 27
2.16 Port Operation ....................................... 27
2.17 Port States ............................................... 27
3 Audio Interface ............................ 29
3.1 Overview ................................................. 29
3.2 Audio PLL ............................................... 29
3.3 I2S Interface ............................................. 30
3.3.1 External DAC .............................. 30
3.3.2 Sample Sizes and Rates ............. 30
3.3.3 Stereo Software Interface ........... 30
3.4 SPDIF INTERFACE ............................... 30
3.5 MAILBOX (DMA CONTROLLER) ..... 31
3.5.1 Mailboxes ..................................... 31
3.5.2 MBOX DMA Operation ............. 31
3.5.3 Software Flow Control ............... 32
3.5.4 Mailbox Error Conditions ......... 32
3.5.5 MBOX-Specific Interrupts ......... 32
4 Register Descriptions ..................33
4.1 DDR Registers ........................................ 34
4.1.1 DDR DRAM Configuration
(DDR_CONFIG) ......................... 34
4.1.2 DDR DRAM Configuration
(DDR_CONFIG2) ....................... 35
4.1.3 DDR Mode Value
(DDR_MODE_REGISTER) ........ 35
4.1.4 DDR Extended Mode Value
(DDR_EXTENDED_MODE_REGIS
TER) .............................................. 35
4.1.5 DDR Control (DDR_CONTROL) 36
4.1.6 DDR Refresh Control and
Configuration (DDR_REFRESH) 36
4.1.7 DDR Read Data Capture Bit Mask
(DDR_RD_DATA_THIS_CYCLE)
36
4.1.8 DQS Delay Tap Control for Byte 0
(TAP_CONTROL_0) .................. 36
4.1.9 DQS Delay Tap Control for Byte 1
(TAP_CONTROL_1) .................. 37
4.1.10 Write Buffer Flush for GE0 Interface
(DDR_WB_FLUSH_GE0) .......... 37
4.1.11 Write Buffer Flush for GE1 Interface
(DDR_WB_FLUSH_GE1) .......... 37
4.1.12 Write Buffer Flush for USB Interface
(DDR_WB_FLUSH_USB) .......... 37
4.1.13 Write Buffer Flush for PCIE
Interface
(DDR_WB_FLUSH_PCIE) ......... 38
4.1.14 DDR2 Configuration
(DDR_DDR2_CONFIG) ............. 38
4.1.15 DDR EMR2 Value (DDR_EMR2) 38
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR7242 Network Processor • 3
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PRELIMINARY
4.1.16 DDR EMR3 Value (DDR_EMR3) 38
4.2 UART Registers ...................................... 39
4.2.1 Receive Buffer (RBR) .................. 39
4.2.2 Transmit Holding (THR) ........... 39
4.2.3 Divisor Latch Low (DLL) .......... 40
4.2.4 Divisor Latch High (DLH) ......... 40
4.2.5 Interrupt Enable (IER) ................ 40
4.2.6 Interrupt Identity (IIR) ............... 41
4.2.7 FIFO Control (FCR) .................... 41
4.2.8 Line Control (LCR) ..................... 42
4.2.9 Modem Control (MCR) .............. 42
4.2.10 Line Status (LSR) ......................... 43
4.2.11 Modem Status (MSR) ................. 44
4.3 GPIO Registers ....................................... 45
4.3.1 General Purpose I/O Output
Enable (GPIO_OE) ...................... 45
4.3.2 General Purpose I/O Input Value
(GPIO_IN) .................................... 45
4.3.3 General Purpose I/O Output Value
(GPIO_OUT) ................................ 46
4.3.4 General Purpose I/O Per Bit Set
(GPIO_SET) ................................. 46
4.3.5 General Purpose I/O Per Bit Clear
(GPIO_CLEAR) ........................... 46
4.3.6 General Purpose I/O Interrupt
Enable (GPIO_INT) .................... 46
4.3.7 General Purpose I/O Interrupt
Type (GPIO_INT_TYPE) ........... 46
4.3.8 General Purpose I/O Interrupt
Polarity (GPIO_INT_POLARITY)
47
4.3.9 General Purpose I/O Interrupt
Pending (GPIO_INT_PENDING) .
47
4.3.10 General Purpose I/O Interrupt
Mask (GPIO_INT_MASK) ......... 47
4.3.11 GPIO Function
(GPIO_FUNCTION_1) ............... 48
4.3.12 General Purpose I/O Input Value
(ETH_LED) .................................. 48
4.3.13 Extended GPIO Function Control
(GPIO_FUNCTION_2) ............... 49
4.4 PLL Control Registers ........................... 50
4.4.1 CPU Phase Lock Loop
Configuration
(CPU_PLL_CONFIG) ................. 51
4.4.2 ETH_USB Phase Lock Loop
Configuration
(ETH_USB_PLL_CONFIG) ....... 52
4.4.3 CPU Clock Configuration
(CPU_CLOCK_CONTROL) ...... 52
4.4.4 PCIE Phase Lock Loop
Configuration
(PCIE_PLL_CONFIG) ................ 53
4.4.5 PCIE PLL Dither Max Limit
(PCIE_PLL_MAX_LIMIT) ......... 53
4.4.6 PCIE PLL Dither Min Limit
(PCIE_PLL_MIN_LIMIT) .......... 54
4.4.7 PCIE PLL Dither Update Step
(PCIE_PLL_DITHER_STEP) ..... 54
4.4.8 LDO Power Control
(LDO_POWER_CONTROL) ..... 54
4.4.9 Current PCIE PLL Dither
(CURRENT_PCIE_PLL_DITHER)
54
4.4.10 ETH_XMII ................................... 55
4.4.11 AUDIO Phase Lock Loop
Configuration
(AUDIO_PLL_CONFIG) ........... 55
4.4.12 Audio PLL Modulation
(AUDIO_PLL_MODULATION) 56
4.4.13 Audio PLL Frequency Control Step
(AUDIO_PLL _MOD_STEP) ..... 56
4.4.14 Current Audio Modulation Logic
Output
(CURRENT_AUDIO_PLL_MODU
LATION) ...................................... 56
4.5 Reset Registers ....................................... 57
4.5.1 General Purpose Timers
(RST_GENERAL_TIMERx) ....... 57
4.5.2 General Purpose Timers Reload
(RST_GENERAL_TIMER_RELOA
Dx) ................................................ 57
4.5.3 Watchdog Timer Control Register
(RST_WATCHDOG_TIMER_CON
TROL) ........................................... 58
4.5.4 Watchdog Timer Register
(RST_WATCHDOG_TIMER) ... 58
4.5.5 Miscellaneous Interrupt Status
(RST_MISC_INTERRUPT_STATUS
) ...................................................... 59
4.5.6 Miscellaneous Interrupt Mask
(RST_MISC_INTERRUPT_MASK)
60
4.5.7 Global Interrupt Status
4 • AR7242 Network Processor
4 April 2011
Atheros Communications, Inc.
COMPANY CONFIDENTIAL



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