AR7100 Datasheet PDF - Atheros

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AR7100
Atheros

Part Number AR7100
Description High Performance And Cost-Effective Network Processor
Page 30 Pages


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Data Sheet
December 2008
AR7100: A Scalable, High Performance And Cost-Effective
Network Processor Family
General Description
Features
The Atheros AR7100 is a scalable, high
performance and cost effective network
processor family that allows efficient design of
solutions addressing triple play services such
as voice, video and data for home and
enterprise access point, router and gateway
applications. It includes a 32-bit MIPS
processor, PCI host interface, two 802.3
Ethernet MACs with GMII/RGMII/RMII/MII
interface, two USB 2.0 MAC/PHYs, a PCM
interface for glueless SLIC support, external
memory interface for serial Flash and DDR-
SDRAM, a high-speed UART, I2S interface, and
GPIOs that can be used for LED controls.
The AR7100 network processor when paired
with the AR9100 chipset family (AR9160
MAC/baseband processor and AR9106/
AR9104/AR9103/AR9102/AR9101 radios)
provides the best in class WLAN solution
capable of supporting 802.11a/b/g/n
standards.
Integrated MIPS 24K-family processor
300–680 MHz processor frequency:
– AR7130, 300 MHz, Fast Ethernet version
– AR7141, 400 MHz, supports Fast
Ethernet and GB Ethernet
– AR7161, 680 MHz, supports Fast
Ethernet and GB Ethernet
High Performance DDR memory controller
(16- or 32-bit)
Dual IEEE 802.3 Ethernet MAC supporting
10/100/1000 Mbps, full and half duplex
and GMII/RGMII/RMII/MII interfaces
Two-port USB 2.0 Host Controllers with
built-in MAC/PHY
UART for console support
32-bit, 33/66 MHz PCI 2.3 host interface
supporting up to three client devices
IEEE 1149.1 standard test access port and
boundary scan architecture supported
JTAG based debugging of the processor
core supported
13 mm x 13 mm 384 TFBGA lead-free
package
Along with the Atheros AR9100 (MAC/BB
and radio chips) family—Completes an all-
CMOS solution for 802.11a/b/g/n WLANs,
supporting extended range for worldwide
operations
System Block Diagram
2.4/5 GHz
3x
FEM
DDR Controller
and Memory
Interface
AR9103/
AR9106
AR9160
AR9100
40
MHz
Crystal
PCI
Interface
MIPS Processor
AR7100
Ethernet MAC
Ethernet MAC
High Speed UART
USB MAC/PHY
USB MAC/PHY
External Interface
PCM Interface
I2S
Serial Flash/DDR Interface
RGMII Interface
RGMII Interface
UART Interface
USB 2.0 Interface
USB 2.0 Interface
GPIOs/LEDs
SLIC
Audio Interface
© 2000-2008 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Atheros XR®, Driving the Wireless Future®, ROCm®, Super
AG®, Super G®, Total 802.11n®, and Wake on Wireless® are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, the Air
is Cleaner at 5-GHz™, XSPAN™, Wireless Future. Unleashed Now.™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a
registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
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Revision History
Revision
November 2008
June 2008
February 2008
January 2007
December 2006
November 2006
September 2006
Description of Changes
Updated Section 5.3, DDR Register, offset address of PCI Window 0 to 7, DDR
GE0, GE1, PCI and USB Flush registers.
Updated registers section
Added SPI registers, added pin direction and voltage information
Updated RMII pin information
Added register descriptions
Updated the multiplexed Ethernet pin information
Updated the general description
Preliminary information
2 • AR7100 Network Processor Family
2 December 2008
Atheros Communications, Inc.
COMPANY CONFIDENTIAL



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Table of Contents
1 Pin Descriptions ............................ 7
2 Functional Description ............... 23
2.1 Address MAP ......................................... 24
2.2 Ethernet ................................................... 25
2.3 Ethernet Connection Diagrams ............ 25
2.4 USB ........................................................... 27
2.5 Audio Interface ...................................... 27
2.5.1 SLIC .............................................. 27
2.5.2 I2S .................................................. 27
2.6 DDR Interface ......................................... 27
2.7 UART ....................................................... 28
2.8 CPU .......................................................... 28
2.9 Processor Frequency .............................. 29
3 Electrical Characteristics ............ 31
3.1 Absolute Maximum Ratings ................ 31
3.1.1 Recommended Operating
Conditions ................................... 31
3.2 General DC Electrical Characteristics . 32
3.3 Power on Sequence Requirements ...... 32
3.4 Typical Power Consumption Parameters
32
4 AC Specifications ........................ 33
4.1 GMII Timing (1000BASE-T) ................. 33
4.1.1 GMII Transmit ............................ 33
4.1.2 GMII Receive ............................... 33
4.2 RGMII Timing ........................................ 34
4.2.1 RGMII Transmit .......................... 34
4.2.2 RGMII Receive ............................ 34
4.3 MII Timing (100 Mbps) ......................... 35
4.4 RMII Timing (100 Mbps) ....................... 35
4.5 GMII, MII, RGMII, RMII Timing Values
35
4.6 PCI Timing .............................................. 36
4.7 DDR Timing ............................................ 37
4.7.1 DDR Address Bus ....................... 37
4.7.2 DQ/DQM/DQS Bus Output .... 37
4.7.3 DQS/DQ Bus Input .................... 38
4.8 Reset Timing ........................................... 38
5 Register Descriptions ..................39
5.1 PCI CSR Registers .................................. 39
5.1.1 Local Configuration Command 39
5.1.2 Local Configuration Write Data 40
5.1.3 Local Configuration Read Data 40
5.1.4 Configuration I/O Address ...... 40
5.1.5 Configuration I/O Command .. 40
5.1.6 Configuration I/O Write Data .. 41
5.1.7 Configuration I/O Read Data .. 41
5.1.8 PCI Error ...................................... 41
5.1.9 PCI Error Address ...................... 42
5.1.10 AHB Error .................................... 42
5.1.11 AHB Error Address .................... 42
5.2 PCI Configuration Registers ................ 42
5.2.1 PCI Command Status
(COMMAND_STATUS) ............ 43
5.2.2 Device Revision ID
(REVISION_ID) .......................... 44
5.2.3 Cache Line Size (CACHE_SZ) .. 44
5.2.4 Memory Base Address
(BASE_ADDR0) .......................... 44
5.2.5 Capabilities Pointer (CAP_PTR) 45
5.2.6 Interrupt Line (INT_LINE) ....... 45
5.2.7 TRDY Timeout Value
(CFG_TIMER) ............................. 45
5.3 DDR Registers ........................................ 46
5.3.1 DDR DRAM Configuration 1
(DDR_CONFIG) ......................... 47
5.3.2 DDR DRAM Configuration 2
(DDR_CONFIG2) ....................... 48
5.3.3 DDR Mode
(DDR_MODE_REGISTER) ........ 48
5.3.4 DDR Extended Mode
(DDR_EXTENDED_MODE_REGIS
TER) .............................................. 49
5.3.5 DDR Control (DDR_CONTROL) 49
5.3.6 DDR Refresh Control and
Configuration (DDR_REFRESH) 49
5.3.7 DDR Read Data Capture Bit Mask
(DDR_RD_DATA_THIS_CYCLE)
50
5.3.8 DQS Delay Tap Control for Byte 0
(TAP_CONTROL_0) .................. 50
5.3.9 DQS Delay Tap Control for Byte 1
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COMPANY CONFIDENTIAL
AR7100 Network Processor Family • 3
December 2008 3



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(TAP_CONTROL_1) .................. 50
5.3.10 PCI Address Space Offset for PCI
Window 0 (PCI_WINDOW_0) . 51
5.3.11 PCI Address Space Offset for PCI
Window 1 (PCI_WINDOW_1) . 51
5.3.12 PCI Address Space Offset for PCI
Window 2 (PCI_WINDOW_2) . 51
5.3.13 PCI Address Space Offset for PCI
Window 3 (PCI_WINDOW_3) . 51
5.3.14 PCI Address Space Offset for PCI
Window 4 (PCI_WINDOW_4) . 52
5.3.15 PCI Address Space Offset for PCI
Window 5 (PCI_WINDOW_5) . 52
5.3.16 PCI Address Space Offset for PCI
Window 6 (PCI_WINDOW_6) . 52
5.3.17 PCI Address Space Offset for PCI
Window 7 (PCI_WINDOW_7) . 52
5.3.18 Write Buffer Flush for GE0
(DDR_WB_FLUSH_GE0) .......... 53
5.3.19 Write Buffer Flush for GE1
(DDR_WB_FLUSH_GE1) .......... 53
5.3.20 Write Buffer Flush for USB
(DDR_WB_FLUSH_USB) .......... 53
5.3.21 Write Buffer Flush for PCI
(DDR_WB_FLUSH_PCI) ........... 53
5.4 UART Registers ...................................... 54
5.4.1 Rx Buffer (UART_RBR); Tx Holding
(UART_THR); Divisor Latch Low
(UART_DLL) ............................... 54
5.4.2 Interrupt Enable (UART_IER);
Divisor Latch High (UART_DLH)
55
5.4.3 Interrupt Identity (UART_IIR);
FIFO Control (UART_FCR) ....... 55
5.4.4 Line Control (UART_LCR) ........ 56
5.4.5 Modem Control (UART_MCR) 56
5.4.6 Line Status (UART_LSR) ........... 57
5.5 USB Control Registers ........................... 58
5.5.1 Frame Length Adjust
(FLADJ_VAL) .............................. 58
5.5.2 USB Host Configuration
(USB_CONFIG) ........................... 59
5.6 GPIO Registers ....................................... 60
5.6.1 GPIO Enable (GPIO_OE) ........... 60
5.6.2 GPIO Input Value (GPIO_IN) ... 60
5.6.3 GPIO Output Value (GPIO_OUT)
61
5.6.4 GPIO Per-Bit Set (GPIO_SET) ... 61
5.6.5 GPIO Per-Bit Clear (GPIO_CLEAR)
61
5.6.6 GPIO Interrupt Enable (GPIO_INT)
61
5.6.7 GPIO Interrupt Type
(GPIO_INT_TYPE) ..................... 62
5.6.8 GPIO Interrupt Polarity
(GPIO_INT_POLARITY) ........... 62
5.6.9 GPIO Interrupt Pending
(GPIO_INT_PENDING) ............ 62
5.6.10 GPIO Interrupt Mask
(GPIO_INT_MASK) ................... 62
5.6.11 GPIO Function
(GPIO_FUNCTION) .................. 63
5.7 PLL Control Registers ........................... 63
5.7.1 CPU Phase Lock Loop
Configuration
(CPU_PLL_CONFIG) ................. 64
5.7.2 Secondary Phase Lock Loop
Configuration
(SEC_PLL_CONFIG) .................. 65
5.7.3 CPU Clock Control
(CPU_CLOCK_CONTROL) ...... 65
5.7.4 Ethernet Internal Clock Control
(ETH_INT0_CLK) ....................... 66
5.7.5 Ethernet Internal Clock Control
(ETH_INT1_CLK) ....................... 66
5.7.6 Ethernet Clock Control
(ETH_EXT_CLK) ........................ 67
5.7.7 PCI Clock Control (PCI_CLK) .. 67
5.8 Reset Registers ....................................... 68
5.8.1 General Purpose Timer
(RST_GENERAL_TIMER) ......... 68
5.8.2 General Purpose Timer Reload
(RST_GENERAL_TIMER_RELOA
D) .................................................. 68
5.8.3 Watchdog Timer Control
(RST_WATCHDOG_TIMER_CON
TROL) ........................................... 69
5.8.4 Watchdog Timer
(RST_WATCHDOG_TIMER) ... 69
5.8.5 Misc. Interrupt Status
(RST_MISC_INTERRUPT_STATUS
) ...................................................... 70
5.8.6 Misc. Interrupt Mask
(RST_MISC_INTERRUPT_MASK)
70
4 • AR7100 Network Processor Family
4 December 2008
Atheros Communications, Inc.
COMPANY CONFIDENTIAL



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