2.1.6. Added SMBus Time-Out Events
The CP2120 offers two additional timers, SCL Low time-out and Free Bus Detect, that, when enabled, allow the
CP2120 to be fully compatible with SMBus specifications. The SCL Low time-out timer monitors the logic level of
SCL. If SCL remains low for longer than 25 milliseconds during an SMBus transaction, the CP2120 terminates the
transaction and indicates the termination source by setting the I2CSTAT status register to “SCL Low Time Out”.
When the Free Bus Detect timer is enabled, the CP2120 considers SMBus bus lines free if SCL has remained high
for at least 50 µs.
Like the SC18IS60x device, the CP2120 receives commands across a SPI bus and then acts as an SMBus bus
master to transmit and receive data with SMBus slaves. The SPI bus is controlled by a SPI master firmware
system, and this system must be modified to ensure reliable communication.
www.DataShee2t4.2U..c1o.mCommands Requiring the CP2120 to Transmit Data Across SPI
The Read Internal Register, Read Buffer, and Revision Number commands cause the CP2120 to transmit data
back to the SPI Master. During these commands, the SPI Master transmits command bytes through the MOSI SPI
pin and then receives bytes through the MISO SPI pin. For these commands, the SPI Master must transmit one
extra data byte after valid command bytes have been transmitted before valid bytes will be output from the
Designers can make this modification to their SPI Master firmware systems in a number of ways. For example, if
the SPI Master transmits commands by pulling bytes from an outgoing SPI data byte buffer, the design can push
one extra byte onto the buffer after the system has pushed all valid bytes to transmit. When the command is
transmitted to the CP2120, the extra byte will be transmitted as well.
2.2.2. SPI Clock Timing
The CP2120’s SPI interface can operate at SCLK frequencies up to 1 MHz. If the current, SC18IS60x-based
design communicates at a SPI clock of frequencies higher than 1 MHz, the CP2120 will not be able to respond
reliably with valid data.
2.2.3. I2CCLOCK Internal Register Values
While the CP2120 can reproduce the same range of SMBus clock frequencies as the SC18IS60x, the CP2120
uses a different equation than the SC18IS60x to map register values to SMBus SCL frequencies. For this reason,
code configuring the SMBus clock frequency will need to be changed. The CP2120 uses the following equation to
determine SMBus clock frequency:
SMBus Clock Frequency (kHz) = I---2---C-----C-2---0-L--0-O-----C-----K--
When porting a SC18IS60x design into a CP2120 design, the schematic and layout must be altered to take into
account the CP2120’s pin-out and package size.
3.1. Schematic Modifications
While CP2120 and SC18IS60x pin names are identical, the CP2120 has more pins to accommodate the additional
features. Updates to the schematic should include adding traces for the extra GPIO pins and the edge-triggered
3.2. Layout Modifications
The CP2120’s pin-out is drastically different from the pin-out of the SC18IS60x, and updates to the layout must
take into account the fact that many signal traces will need to be routed to different pins. For instance, the
SC18IS60x SCLK trace is routed to pin 11, but the CP2120 routes that signal to pin 1.
The footprints for the SC18IS60x and the CP2120 also differ. The SC18IS60x uses a TSSOP16 package, while the
CP2120 uses a smaller QFN-20 package.