AM486DX5 Datasheet PDF - AMD

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AM486DX5
AMD

Part Number AM486DX5
Description Microprocessor Family
Page 30 Pages


AM486DX5 datasheet pdf
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PRELIMINARY
Enhanced Am486®DX
Microprocessor Family
DISTINCTIVE CHARACTERISTICS
s High-Performance Design
- Industry-standard write-back cache support
- Frequent instructions execute in one clock
- 105.6-million bytes/second burst bus at 33 MHz
www.DataSheet4U-.comFlexible write-through and write-back address
control
- Advanced 0.35-µ CMOS-process technology
- Dynamic bus sizing for 8-, 16-, and 32-bit buses
- Supports “soft reset” capability
s High On-Chip Integration
- 16-Kbyte unified code and data cache
- Floating-point unit
- Paged, virtual memory management
s Enhanced System and Power Management
- Stop clock control for reduced power
consumption
- Industry-standard two-pin System Management
Interrupt (SMI) for power management indepen-
dent of processor operating mode and operating
system
- Static design with Auto Halt power-down support
- Wide range of chipsets supporting SMM avail-
able to allow product differentiation
s Complete 32-Bit Architecture
- Address and data buses
- All registers
- 8-, 16-, and 32-bit data types
s Standard Features
- 3-V core with 5-V tolerant I/O
- Wide range of chipsets and support available
through the AMD FusionE86SM Program
s 168-Pin PGA Package or 208-Pin SQFP Package
s IEEE 1149.1 JTAG Boundary-Scan Compatibility
GENERAL DESCRIPTION
The Enhanced Am486®DX Microprocessor Family is an
addition to the AMD E86 family of embedded micropro-
cessors. This new family enhances system performance
by incorporating a 16-Kbyte write-back cache to the ex-
isting flexible clock control and enhanced SMM features
of a 486 CPU.
The Enhanced Am486DX microprocessor family en-
ables write-back configuration through software and
cacheable access control. On-chip cache lines are con-
figurable as either write-through or write-back. The CPU
clock control feature permits the CPU clock to be stopped
under controlled conditions, allowing reduced power
consumption during system inactivity. The SMM function
is implemented with an industry standard two-pin inter-
face.
Since the Enhanced Am486DX microprocessor family is
supported as an embedded product, customers can rely
on continued cost reduction, a long-term supply, and
extended temperature products.
In addition, customers have access to a large selection
of inexpensive development tools, compilers, and
chipsets. A large number of PC operating systems and
Real Time Operating Systems (RTOS) support the En-
hanced Am486DX microprocessor family. This results in
decreased development costs and improved time to mar-
ket.
Table 1 shows available processors in the Enhanced
Am486DX microprocessor family. See page 54 for in-
formation on how these parts differ from other Am486
processors.
Table 1. Clocking Options
Operating
Frequency
Am486DX5-133
Am486DX5-133
Am486DX4-100
Am486DX4-100
Am486DX2-66
Am486DX2-66
Input Clock
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
Available Package
168-pin PGA
208-pin SQFP
168-pin PGA
208-pin SQFP
168-pin PGA
208-pin SQFP
This document contains information on a product under development at Advanced Micro Devices. The information is
intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication # 20736 Rev: B Amendment/0
Issue Date: March 1997



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BLOCK DIAGRAM
PRELIMINARY
32-Bit Data Bus
32-Bit Data Bus
32-Bit Linear Address
Barrel Shifter
Segmentation
Unit
www.DataSheet4U.coRmegister File
ALU
24
Physical
Address
Descriptor
Registers
Limit and
Attribute
PLA
PCD, PWT
Paging Unit
2
Translation
Lookaside
Buffer
24
Physical
Address
Cache Unit
16-Kbyte
Cache
128
Micro-instruction
Floating
Point
Unit
Floating
Point
Register
File
Central and
Protection
Test Unit
Control
ROM
Displacement Bus
32
Code
Stream
Instruction
Decode
Decoded
Instruction
Path
24
Prefetcher
32-Byte
Code Queue
2x16 Bytes
Power
Plane
VOLDET
VCC, Vss
Clock
Interface
Clock
Generator
CLK
CLKMUL
STPCLK
Bus Interface
32
Address
Drivers
Write
Buffers
4x32
Copyback
Buffers
4x32
Writeback
Buffers
4x32
Data Bus
32 Transceivers
A31–A2
BE3–BE0
D31–D0
Bus Control
Request
Sequencer
ADS, W/R, D/C,
M/IO, PCD, PWT,
RDY, LOCK,
PLOCK, BOFF,
A20M, BREQ,
HOLD, HLDA,
RESET, INTR,
NMI, FERR, UP,
IGNNE, SMI,
SMIACT, SRESET
Burst Bus
Control
Bus Size
Control
BRDY, BLAST
BS16, BS8
Cache
Control
KEN, FLUSH,
AHOLD, CACHE,
EADS, INV,
WB/WT, HITM
Parity
Generation
and Control
JTAG
PCHK,
DP3–DP0
TDI, TCK,
TDO, TMS
2 Enhanced Am486DX Microprocessor Family



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LOGIC SYMBOL
PRELIMINARY
Clock
Stop Clock
Clock Multiplier
Address Mask
Upgrade
Present
Voltage Detect
Address Bus
www.DataSheet4U.com
28
2
4
Bus Cycle
Control
Bus Cycle
Definition
CLK
STPCLK
CLKMUL
A20M
UP
VOLDET
A31–A4
A3–A2
BE3–BE0
BS8
BS16
ADS
RDY
M/IO
D/C
W/R
LOCK
PLOCK
Interrupts
INTR
NMI
RESET
SRESET
Enhanced Am486DX
CPU
D31–D0 32
DP3–DP0
PCHK
BRDY
BLAST
CACHE
SMI
SMIACT
4
PWT
PCD
WB/WT
INV
KEN
FLUSH
AHOLD
EADS
HITM
HOLD BOFF
BREQ HLDA
IGNNE FERR
TCK TDI
TMS TDO
Data Bus
Data Parity
Burst
Control
SMM
Page
Cacheability
Cache Control/
Invalidation
Bus Arbitration
Numeric Error
Reporting
IEEE Test
Port Access
Enhanced Am486DX Microprocessor Family
3



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ORDERING INFORMATION
Standard Products
PRELIMINARY
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
AM486 DX 5 –133 W 16 B H C
www.DataSheet4U.com
Temperature Range
C = Commercial (Tcase = 0°C to +85°C)
I = Industrial (Tcase = –40°C to +100°C)
Package Type
H =208-lead Shrink Quad Flat Pack (PDE-208)
G = 168-pin Pin Grid Array (CGM-168)
Cache Type
B = Write-back (also supports write-through)
Cache Size
16 = 16 Kbyte
Voltage Range
V = 3.3 V ± 0.3 V
W = 3.45 V ± 0.15 V
Speed Option
–133 =133 MHz (5-class performance)
–100 =100 MHz
– 66 = 66 MHz
Processor Type
DX2 =Clock-doubled with FPU
DX4 =Clock-tripled with FPU
DX5 =Clock-quadrupled with FPU
Processor Family
Am486 high-performance CPU
Valid Combinations
AM486DX2-66V16B
AM486DX4-100V16B
AM486DX5-133W16B
AM486DX5-133V16B
HC
GC
HI
GI
HC
GC
HI
GI
HC
GC
HC
GC
Valid Combinations
Valid Combinations list configura-
tions planned to be supported in vol-
ume for this device. Consult the local
AMD sales office to confirm avail-
ability of specific valid combinations
and to check on newly released
combinations.
4 Enhanced Am486DX Microprocessor Family



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