ALM-81224 Datasheet PDF - AVAGO

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ALM-81224
AVAGO

Part Number ALM-81224
Description High Linearity 1450 - 2750 MHz Variable Gain Amplifier
Page 23 Pages


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ALM-81224
High Linearity 1450 – 2750 MHz Variable Gain Amplifier
Data Sheet
Description
Avago Technologies’ ALM-81224 is a high linearity vari-
able-gain amplifier module for use in the 1450-2750MHz
band. Gain control is achieved using a single DC voltage
input pin. High linearity is achieved through the use of
Avago Technologies’ proprietary GaAs Enhancement-
mode pHEMT process1. It is housed in a miniature 6.0
x 6.0 x 1.0 mm 24-pin Molded Chip On Board (MCOB)
package. Gain changes monotonically with gain control
pin voltage. Input is fully matched. Output match can be
tuned for optimal performance at a particular frequency
band within the VGA operation frequency range using
common RF board layout. The compact footprint coupled
with high linearity and efficiency makes ALM-81224 an
ideal choice for Basestation transmitters and receivers and
Temperature Compensation Circuitry applications.
Component Image
(6.0 x 6.0 x 1.0) mm 24-lead MCOB
AVAGO
81224
WWYY
XXXX
Note:
Package marking provides
orientation and identification
“81224 “ = Device Code
“WWYY” = Date Code identifies
month and year of
manufacturing
“XXXX” = Last 4 digit of assembly
lot number
Pin Configuration
Vdd1 GND GND GND GND Vdd2
24 23 22 21 20 19
GND 1
18 GND
RFIN 2
Q1/Q2 3
Interstage
4
GROUND
17 ½
¾ RFOUT
16 ¿
15 GND
GND 5
14 GND
GND 6
13 GND
7 8 9 10 11 12
Vc_att GND Vc1 Vc2 GND Vddbias
Features
x High Linearity at low bias current
x High max gain: 23.8 dB typ
x High linearity performance: +16.5 dBm at -65 dBc ACLR
using dual-carrier W-CDMA input signal
x Fully-matched 50 Ohm input and simple output match
x Low Noise Figure
x Built-in attenuator with monotonic response
x Variable Gain range: 38 dB typ
x GaAs E-pHEMT Technology [1]
x Small package size: 6.0 x 6.0 x 1.0 mm
Typical Performances
2140 MHz @ 5 V, 383 mA (typ)
x 23.8 dB Gain at minimum attenuation
x +16.5 dBm output power (-65 dBc ACLR) using dual-
carrier W-CDMA input signal with PAPR = 7.5 dB.
x NF: 2dB @ max gain and 16 dB @ min gain
x P1dB: 27.4 dBm
x Attenuator range: 38 dB with Vc_att: (0 V – 3.3 V)
x Shutdown current (Vc1, Vc2 = 0 V): < 30 PA
Applications
x Basestation Transmitter, Receiver and Temperature
Compensation Circuits requiring continuously variable
gain functionality
Note:
1. Enhancement mode technology employs positive Vgs, thereby
eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 50 V
ESD Human Body Model = 500 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.



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Table 1. ALM-81224 Absolute Maximum Rating [1]
Symbol
Vdd,max
Vctrl,max
Ids,max
Pd
Pin
Tj
Tstg
Parameter
Units
Drain Voltage, RF output to ground V
Control Voltage [4]
V
Device Drain Current
mA
Power Dissipation [2]
W
CW RF Input Power
dBm
Junction Temperature
°C
Storage Temperature
°C
Absolute Maximum
5.5
5.5
500
2.75
22
150
-65 to 150
Thermal Resistance
Thermal Resistance [3]
(Vd = 5.0 V, Id = 320 mA, Tc = 85°C)
Tjc = 20°C/W
Notes:
1. Operation of this device in excess of any of
these limits may cause permanent damage.
2. Ground Paddle temperature is 25° C. Derate
50 mW/°C for Tc > 95° C.
3. Thermal resistance measured using 150° C
Infra-Red Microscopy Technique.
4. Vc1/Vc2 ≤ Vdd1/Vdd2.
Table 2. Electrical Specifications
TA = 25° C, Vdd1 = Vdd2 = VBias = 5 V @ total quiescent current of 383 mA, RF performance at 2140 MHz, CW operation
unless otherwise stated.
Symbol
Parameter and Test Condition
Units Freq. Min.
Typ.
Vdd Supply Voltage
5
Idq_total
Quiescent Supply Current
mA 290 383
Freq Operating Frequency Range
MHz 1450
Max Gain
Max Gain (minimum attenuation) (1)
dB
1485
27.0
1840
24.9
1960
24.8
2140
22.2
23.8
2650
21.5
NF Noise Figure (minimum attenuation)
dB
2
OP1dB
Output Power at 1dB Gain Compression [1]
dBm 1485 –
1840
1960
2140
24.7
2650
28.0
27.7
28.7
27.4
28.3
OIP3
Output Third Order Intercept Point [2]
dBm
44
ACLR
ACLR at linear Pout = 12 dBm with dual-carrier
W-CDMA input signal [1,3]
dBc 1485
1840
1960
2140
2650
-67.1
-68.4
-67.6
-66.6
-67.5
Ilinear_total Total current draw at Plinear level
mA 290 383
S11 Input Return Loss, 50 : source
dB 2140
-15
S22 Output Return Loss, 50 : load
dB 2140
-10
S12 Reverse Isolation
dB 2140
40
Atten
Gain attenuation range, Vc_att: (0 V – 3.3 V)
dB
38
Notes:
1. Measured with output match tuned to frequency as specified. See Table 3 for component values.
2. OIP3 test condition: FRF1 - FRF2 = 1 MHz with input power of -8 dBm per tone measured at worst side band.
3. Peak-to-average power ratio = 7.5 dB. Measured on Agilent MXA N9020A with low-noise option. Refer to Figure 77 for CCDF.
Max.
460
2750
-63.5
460
2



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ALM-81224 Consistency Distribution Charts
LSL USL
LSL
220 260 300 340 380 420 460 500 540
Figure 1. Idd_total at Vdd = 5 V; LSL = 290 mA, Nominal = 383 mA,
USL= 460 mA
22 22.4 22.8 23.2 23.6 24 24.4 24.8 25.2
Figure 2. Max gain at 2140 MHz; LSL = 22.2 dB, Nominal = 23.8 dB
LSL USL
25 26 27 28 29 30 31 -69.5 -69 -68.5 -68 -67.5 -67 -66.5 -66 -65.5 -65 -64.5 -64 -63.5
Figure 3. OP1dB; LSL = 24.7 dBm, Nominal = 27.4 dBm
Figure 4. ACLR (Dual-Carrier Signal) at 12 dBm output power;
Nominal = -66.6 dBc, USL = -63.5 dBc
3



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Typical DC Performance Plots
TA = 25° C, Vdd = Vdd2 = VBias = 5 V @ 383 mA, RF performance tuned at 2140 MHz using demoboard of Figure 71.
CW operation unless otherwise stated. Dual Carrier Signal uses W-CDMA modulation with 7.5 dB crest factor. Refer
to Figure 77 for CCDF. Single Carrier Signal uses WCDMA Test Tone #1.
2.4
2.1
1.8
1.5
1.2
0.9
0.6 25° C
0.3
-40° C
85° C
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vcatt (V)
Figure 5. Ic_att Vs Vc_att
0.21
0.18
0.15
0.12
0.09
0.06
25° C
0.03 -40° C
85° C
0.00
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vc1 (V)
Figure 6. Idd1 Vs Vc1
Vddbias = 5 V, Vc2 = 0 V, Vdd1 = Vdd2 = 5 V, Vc_att = 0 V
0.35
0.30
0.25
0.20
0.15
0.10
25° C
0.05 -40° C
85° C
0.00
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vc2 (V)
Figure 7. Idd2 Vs Vc2
Vddbias = 5 V, Vc1 = 0 V, Vdd1 = Vdd2 = 5 V, Vc_att = 0 V
4



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