ADuC7121 Datasheet PDF - Analog Devices

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ADuC7121
Analog Devices

Part Number ADuC7121
Description Precision Analog Microcontroller 12-Bit Analog I/O ARM7TDMI MCU
Page 30 Pages


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Precision Analog Microcontroller, 12-Bit
Analog I/O, ARM7TDMI MCU
ADuC7121
FEATURES
Software-triggered in-circuit reprogrammability
Analog input/output
9-channel, 12-bit, 1 MSPS ADC
2 differential pairs with input PGA
7 general-purpose inputs (differential or single-ended)
Fully differential and single-ended modes
0 V to VREF analog input range
5 low noise current digital-to-analog converters (IDACs)
250 mA, 200 mA, 80 mA, 45 mA, 20 mA
4 × 12-bit voltage output DACs
On-chip voltage reference
On-chip temperature sensor
Microcontroller
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Clocking options
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 41.78 MHz
On-chip peripherals
UART, 2 × I2C and SPI serial I/O
32-pin GPIO port
4× general-purpose timers
Wake-up and watchdog timers (WDT)
Power supply monitor
Vectored interrupt controller for FIQ and IRQ
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
Power
Specified for 3 V operation
Active mode: 11 mA at 5 MHz, 40 mA at 41.78 MHz
Packages and temperature range
7 mm × 7 mm 108-ball CSP_BGA
Fully specified for –10°C to +95°C operation
Tools
Low cost QuickStart development system
Full third party support
41.78 MHz PLL with programmable divider
Memory
126 kB flash/EE memory, 8 kB SRAM
APPLICATIONS
Optical modules—tunable laser
In-circuit download, JTAG-based debug
FUNCTIONAL BLOCK DIAGRAM
AVDD 3.3V AGND
DAC0 DAC1 DAC2 DAC3
IDAC0 IDAC1 IDAC2 IDAC3 IDAC4
PADC0N
PADC0P
PADC1N
PADC1P
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10/AINCM
PGA
PGA
TEMPERATURE
SENSOR
ADuC7121
1MSPS
12-BIT
SAR ADC
OSC
WAKE-UP
TIMER
WD
TIMER
VIC
PLA
PLL
POR
PWM
3× GP
TIMERS
126kB
FLASH
(63k ×
16-BIT)
8kB SRAM
(2k × 32-BIT) LDO
ARM7
TDMI
UART
JTAG
GPIO
CONTROL
SPI
I2C × 2
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INTERNAL
REFERENCE
BUF
VREF_1.2 VREF_2.5
P0.0 TO P0.7
P1.0 TO P1.7
Figure 1.
P2.0 TO P2.7
P3.0 TO P3.7
IOVDD
IOGND
XTALI
XTALO
RST
TDO
TDI
TCK
TMS
TRST
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.



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ADuC7121
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications..................................................................................... 5
Timing Specifications ................................................................ 10
Absolute Maximum Ratings.......................................................... 15
ESD Caution................................................................................ 15
Pin Configuration and Function Descriptions........................... 16
Terminology .................................................................................... 20
ADC Specifications .................................................................... 20
DAC Specifications..................................................................... 20
Overview of the ARM7TDMI Core............................................. 21
Thumb Mode (T)........................................................................ 21
Long Multiply (M)...................................................................... 21
EmbeddedICE (I) ....................................................................... 21
Exceptions ................................................................................... 21
ARM Registers ............................................................................ 22
Interrupt Latency........................................................................ 22
Memory Organization ................................................................... 23
Memory Access........................................................................... 23
Flash/EE Memory....................................................................... 23
SRAM ........................................................................................... 23
Memory Mapped Registers ....................................................... 23
Complete MMR Listing............................................................. 24
ADC Circuit Overview .................................................................. 27
ADC Transfer Function............................................................. 27
Temperature Sensor ................................................................... 29
Converter Operation.................................................................. 31
Driving the Analog Inputs ........................................................ 33
Band Gap Reference................................................................... 33
Power Supply Monitor ............................................................... 34
Nonvolatile Flash/EE Memory ..................................................... 35
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Flash/EE Memory Overview..................................................... 35
Flash/EE Memory....................................................................... 35
Flash/EE Memory Security ....................................................... 35
Flash/EE Control Interface........................................................ 36
Execution Time from SRAM and FLASH/EE ........................ 39
Reset and Remap ........................................................................ 39
Other Analog Peripherals.............................................................. 41
Digital-to-Analog Converters................................................... 41
LDO (Low Dropout Regulator)................................................ 43
Current Output DACs (IDAC)................................................. 43
IDAC MMRs ............................................................................... 45
Oscillator and PLL—Power Control........................................ 46
Digital Peripherals.......................................................................... 50
PWM General Overview........................................................... 50
PWM Convert Start Control .................................................... 52
General-Purpose Input/Output.................................................... 53
UART Serial Interface .................................................................... 58
Baud Rate Generation................................................................ 58
UART Register Definition......................................................... 58
I2C Peripherals ................................................................................ 63
Serial Clock Generation ............................................................ 63
I2C Bus Addresses....................................................................... 63
I2C Registers ................................................................................ 64
I2C Common Registers .............................................................. 72
Serial Peripheral Interface ............................................................. 73
SPI MISO (Master In, Slave Out) Pin...................................... 73
SPI MOSI (Master Out, Slave In) Pin...................................... 73
SPICLK (Serial Clock I/O) Pin................................................. 73
SPI Chip Select Input Pin .......................................................... 73
Configuring External Pins for SPI Functionality................... 73
SPI Registers................................................................................ 73
Programmable Logic Array (PLA)............................................... 76
PLA MMRs Interface................................................................. 77
Interrupt System ............................................................................. 80
Normal Interrupt Request (IRQ) ............................................. 80
Fast Interrupt Request (FIQ) .................................................... 81
External Interrupts (IRQ0 to IRQ3) ........................................ 85
Timers .............................................................................................. 87
Timer0—Lifetime Timer........................................................... 87
Timer1—General-Purpose Timer ........................................... 88
Timer2—Wake-Up Timer......................................................... 90
Timer3—Watchdog Timer........................................................ 91
Timer4—General-Purpose Timer ........................................... 93
Outline Dimensions ....................................................................... 95
Ordering Guide .......................................................................... 95
Rev. 0 | Page 2 of 96



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REVISION HISTORY
1/11—Revision 0: Initial Version
ADuC7121
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Rev. 0 | Page 3 of 96



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ADuC7121
GENERAL DESCRIPTION
The ADuC7121 is a fully integrated, 1 MSPS, 12-bit data acquisi-
tion system incorporating a high performance multichannel ADC,
16-bit/32-bit MCU, and Flash®/EE memory on a single chip.
The ADC consists of up to seven single-ended inputs and two
extra differential input pairs. The two differential pair inputs
can be routed through a programmable gain amplifier (PGA).
The ADC can operate in single-ended or differential input mode.
The ADC input voltage is 0 V to VREF. A low drift band gap ref-
erence, temperature sensor, and voltage comparator complete the
ADC peripheral set.
The ADuC7121 provides five current output digital-to-analog
converters (DACs). The current sources (five current DACs)
feature low noise and low drift high-side current output at
11-bit resolution. The five IDACs are as follows: IDAC0 with
250 mA full-scale (FS) output, IDAC1 with 200 mA FS output,
IDAC2 with 80 mA FS output, IDAC3 with 45 mA FS output,
and IDAC4 with 20 mA FS output.
The ADuC7121 also contains four voltage output digital-to-analog
converters (DACs). The DAC output range is programmable to one
of three voltage ranges.
The devices operate from an on-chip oscillator and a PLL
generating an internal high frequency clock of 41.78 MHz
(UCLK). This clock is routed through a programmable clock
divider from which the MCU core clock operating frequency
is generated. The microcontroller core is an ARM7TDMI®,
16-bit/32-bit RISC machine, which offers up to 41 MIPS peak
performance. Eight kB of SRAM and 126 kB of nonvolatile
Flash/EE memory are provided on chip. The ARM7TDMI core
views all memory and registers as a single linear array.
On-chip factory firmware supports in-circuit serial download
via the I2C serial interface port; nonintrusive emulation is also
supported via the JTAG interface. These features are incorporated
into a low cost QuickStart™ development system supporting this
MicroConverter® family.
The device operates from 3.0 V to 3.6 V, and it is specified over
an industrial temperature range of −10°C to +95°C. The IDACs
are powered from a separate 2 V input power supply. When
operating at 41.78 MHz, the power dissipation is typically
120 mW. The ADuC7121 is available in a 108-ball chip scale
package ball grid array [CSP_BGA].
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Rev. 0 | Page 4 of 96



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