ADXRS453 Datasheet PDF - Analog Devices

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ADXRS453
Analog Devices

Part Number ADXRS453
Description High Performance / Digital Output Gyroscope
Page 30 Pages


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FEATURES
Complete rate gyroscope on a single chip
±300°/sec angular rate sensing
Ultrahigh vibration rejection: 0.01°/sec/g
Excellent 16°/hour null bias stability
Internal temperature compensation
2000 g powered shock survivability
SPI digital output with 16-bit data-word
Low noise and low power
3.3 V to 5 V operation
−40°C to +105°C operation
Ultrasmall, light, and RoHS compliant
Two package options
Low cost SOIC_CAV package for yaw rate (z-axis) response
Innovative ceramic vertical mount package (LCC_V), which
can be oriented for pitch, roll, or yaw response
APPLICATIONS
Rotation sensing in high vibration environments
Rotation sensing for industrial and instrumentation
applications
High performance platform stabilization
High Performance,
Digital Output Gyroscope
ADXRS453
GENERAL DESCRIPTION
The ADXRS453 is an angular rate sensor (gyroscope) intended
for industrial, instrumentation, and stabilization applications in
high vibration environments. An advanced, differential, quad
sensor design rejects the influence of linear acceleration, enabling
the ADXRS453 to offer high accuracy rate sensing in harsh envi-
ronments where shock and vibration are present.
The ADXRS453 uses an internal, continuous self-test architec-
ture. The integrity of the electromechanical system is checked by
applying a high frequency electrostatic force to the sense structure
to generate a rate signal that can be differentiated from the base-
band rate data and internally analyzed.
The ADXRS453 is capable of sensing an angular rate of up to
±300°/sec. Angular rate data is presented as a 16-bit word that
is part of a 32-bit SPI message.
The ADXRS453 is available in a 16-lead plastic cavity SOIC
(SOIC_CAV) and an SMT-compatible vertical mount package
(LCC_V), and is capable of operating across a wide voltage
range (3.3 V to 5 V).
CP5
VX
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
GENERATION
HV DRIVE
CLOCK
PHASE- DIVIDER
LOCKED
LOOP AMPLITUDE
DETECT
BAND-PASS
FILTER
12-BIT
ADC
Z-AXIS ANGULAR
RATE SENSOR
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Q DAQ
P DAQ
ADXRS453
DEMOD
Q FILTER
SELF-TEST
CONTROL
ARITHMETIC
LOGIC UNIT
DECIMATION
FILTER
TEMPERATURE
CALIBRATION
FAULT
DETECTION
EEPROM
Figure 1.
LDO
REGULATOR
PDD
DVDD
AVDD
SPI
INTERFACE
MOSI
MISO
SCLK
CS
DVSS
PSS
AVSS
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.



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ADXRS453
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
Absolute Maximum Ratings............................................................ 4 
Thermal Resistance ...................................................................... 4 
Rate Sensitive Axis ....................................................................... 4 
ESD Caution.................................................................................. 4 
Pin Configurations and Function Descriptions ........................... 5 
Typical Performance Characteristics ............................................. 7 
Theory of Operation ........................................................................ 9 
Continuous Self-Test.................................................................... 9 
Mechanical Performance ............................................................... 10 
Noise Performance ......................................................................... 11 
Applications Information .............................................................. 12 
Calibrated Performance............................................................. 12 
Mechanical Considerations for Mounting .............................. 12 
REVISION HISTORY
1/11—Revision 0: Initial Version
Application Circuits ................................................................... 12 
ADXRS453 Signal Chain Timing............................................. 13 
SPI Communication Protocol....................................................... 14 
Command/Response ................................................................. 14 
Device Data Latching................................................................. 15 
SPI Timing Characteristics ....................................................... 16 
Command/Response Bit Definitions....................................... 17 
Fault Register Bit Definitions ................................................... 18 
Recommended Start-Up Sequence with CHK Bit Assertion . 20 
Rate Data Format............................................................................ 21 
Memory Map and Registers .......................................................... 22 
Memory Map .............................................................................. 22 
Memory Register Definitions ................................................... 23 
Package Orientation and Layout Information............................ 25 
Solder Profile............................................................................... 27 
Package Marking Codes ............................................................ 28 
Outline Dimensions ....................................................................... 29 
Ordering Guide .......................................................................... 30 
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Rev. 0 | Page 2 of 32



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ADXRS453
SPECIFICATIONS
TA = TMIN to TMAX, PDD = 5 V, angular rate = 0°/sec, bandwidth = f0/200 (~77.5 Hz), ±1 g, continuous self-test on.
Table 1.
Parameter
MEASUREMENT RANGE
SENSITIVITY
Nominal Sensitivity
Sensitivity Tolerance
Nonlinearity 1
Cross-Axis Sensitivity2
NULL ACCURACY
NOISE PERFORMANCE
Rate Noise Density
LOW-PASS FILTER
Cutoff (−3 dB) Frequency
Group Delay3
SENSOR RESONANT FREQUENCY
SHOCK AND VIBRATION IMMUNITY
Sensitivity to Linear Acceleration
Vibration Rectification
SELF-TEST
Magnitude
Fault Register Threshold
Sensor Data Status Threshold
Frequency
ST Low-Pass Filter
Cutoff (−3 dB) Frequency
Group Delay3
SPI COMMUNICATIONS
Clock Frequency
Voltage Input High
Voltage Input Low
Voltage Output Low
Voltage Output High
Pull-Up Current
MEMORY REGISTERS
Temperature Register
Value at 45°C
Scale Factor
Quadrature, Self-Test, and Rate
Registers
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POWER SUPPLY
Supply Voltage
Quiescent Supply Current
Turn-On Time
Test Conditions/Comments
Full-scale range
See Figure 2
TA = −40°C to +105°C
Best fit straight line
TA = 25°C
TA = −40°C to +105°C
TA = 25°C
TA = 105°C
f0/200
f = 0 Hz
DC to 5 kHz
See the Continuous Self-Test section
Compared to LOCSTx register data
Compared to LOCSTx register data
f0/32
f0/8000
MOSI, CS, SCLK
MOSI, CS, SCLK
MISO, current = 3 mA
MISO, current = −2 mA
CS, PDD = 3.3 V, CS = PDD × 0.15
CS, PDD = 5 V, CS = PDD × 0.15
See the Memory Register Definitions section
Power-on to 0.5°/sec of final value
Symbol
FSR
fLP
tLP
f0
fST
PDD
IDD
Min
±300
−3
−3
3.25
13
2239
1279
52
0.85 × PDD
−0.3
PDD − 0.5
3.15
Typ
80
0.05
±0.4
±0.5
0.015
0.023
77.5
4
15.5
0.01
0.0002
2559
485
1.95
64
60
80
0
5
80
6.0
100
1 Maximum limit is guaranteed by Analog Devices, Inc., characterization.
2 Cross-axis sensitivity specification does not include effects due to device mounting on a printed circuit board (PCB).
3 Minimum and maximum limits are guaranteed by design.
Rev. 0 | Page 3 of 32
Max
±400
Unit
°/sec
LSB/°/sec
+3 %
% FSR rms
+3 %
°/sec
°/sec
°/sec/√Hz
°/sec/√Hz
Hz
4.75 ms
19 kHz
°/sec/g
°/sec/g2
2879
3839
LSB
LSB
LSB
Hz
Hz
76 ms
8.08
PDD + 0.3
PDD × 0.15
0.5
200
300
MHz
V
V
V
V
μA
μA
LSB
LSB/°C
LSB/°/sec
5.25 V
8.0 mA
ms



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ADXRS453
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Acceleration (Any Axis, 0.5 ms)
Unpowered
Powered
Supply Voltage (PDD)
Output Short-Circuit Duration
(Any Pin to Ground)
Operating Temperature Range
LCC_V Package
SOIC_CAV Package
Storage Temperature Range
LCC_V Package
SOIC_CAV Package
Rating
2000 g
2000 g
−0.3 V to +6.0 V
Indefinite
−55°C to +125°C
−40°C to +125°C
−65°C to +150°C
−40°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, for a device
soldered in a printed circuit board (PCB) for surface-mount
packages.
Table 3. Thermal Resistance
Package Type
16-Lead SOIC_CAV (RG-16-1)
14-Lead Ceramic LCC_V (EY-14-1)1
θJA
191.5
185.5
θJC
25
23
Unit
°C/W
°C/W
1 Thermal resistance of the LCC_V package is for the vertical layout, not the
horizontal layout.
RATE SENSITIVE AXIS
The ADXRS453 is available in two package options.
The SOIC_CAV package is for applications that require
z-axis (yaw) rate sensing.
The LCC_V (vertical mount) package is for applications
that require x-axis or y-axis (pitch or roll) rate sensing and
for applications that require z-axis (yaw) rate sensing. The
package has leads on two faces such that it can be mounted
vertically for pitch or roll sensing or horizontally for yaw
sensing.
See Figure 2 for details.
RATE
AXIS
Z-AXIS
+
9
SOIC PACKAGE
16
RATE
AXIS
+
LCC_V PACKAGE
Figure 2. Rate Signal Increases with Clockwise Rotation
ESD CAUTION
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Rev. 0 | Page 4 of 32



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