ADSP-21489 Datasheet PDF - Analog Devices

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ADSP-21489
Analog Devices

Part Number ADSP-21489
Description SHARC Processor
Page 30 Pages


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SHARC Processor
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip
ROM
Up to 450 MHz operating frequency
Code compatible with all other members of the SHARC family
The ADSP-2148x processors are available with unique audio-
centric peripherals, such as the digital applications
interface, serial ports, precision clock generators, S/PDIF
transceiver, asynchronous sample rate converters, input
data port, and more
For complete ordering information, see Ordering Guide on
Page 66
Qualified for automotive applications
SIMD Core
Instruction
Cache
5 Stage
Sequencer
DAG1/2
Core
Timer
PEx PEy
FLAGx/IRQx/
TMREXP
JTAG THERMAL
DIODE
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
DMD
64-BIT
S
DMD
64-BIT
Core Bus
PMD
64-BIT
Cross Bar
PMD 64-BIT
EPD BUS 64-BIT
PERIPHERAL BUS
32-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D
64-BIT
IOD1
32-BIT
PERIPHERAL BUS
CORE
FLAGS/
PWM3-1
PCG
C-D
TIMER
1-0
TWI
SPI/B UART
IOD0 BUS
S/PDIF PCG
Tx/Rx A-D
ASRC PDAP/ SPORT
3-0 IDP 7-0
7-0
FFT
FIR
IIR
DTCP/
MTM
SPEP BUS
CORE PWM
WDT FLAGS 3-0
EP
AMI
SDRAM
CTL
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
Figure 1. Functional Block Diagram
External Port Pin MUX
Peripherals
External
Port
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
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Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
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Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
TABLE OF CONTENTS
General Description ................................................. 3
Family Core Architecture ........................................ 4
Family Peripheral Architecture ................................ 7
I/O Processor Features ......................................... 10
System Design .................................................... 11
Development Tools ............................................. 12
Additional Information ........................................ 13
Related Signal Chains .......................................... 13
Pin Function Descriptions ....................................... 14
Specifications ........................................................ 18
Operating Conditions .......................................... 18
Electrical Characteristics ....................................... 19
Absolute Maximum Ratings .................................. 21
ESD Sensitivity ................................................... 21
Maximum Power Dissipation ................................. 21
Package Information ............................................ 21
Timing Specifications ........................................... 22
Output Drive Currents ......................................... 55
Test Conditions .................................................. 55
Capacitive Loading .............................................. 55
Thermal Characteristics ........................................ 56
100-LQFP_EP Lead Assignment ................................ 58
176-Lead LQFP_EP Lead Assignment ......................... 60
Outline Dimensions ................................................ 64
Surface-Mount Design .......................................... 65
Automotive Products .............................................. 66
Ordering Guide ..................................................... 66
REVISION HISTORY
6/15—Revision B to Revision C
Added footnote to Table 2, ADSP-2148x Family Features ...3
Corrected tWDE Switching Characteristic in AMI Write .... 35
Added four models to Automotive Product Table (Table 63)
in Automotive Products ........................................... 66
Changes to Ordering Guide ....................................... 66
Rev. C | Page 2 of 68 | June 2015



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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
GENERAL DESCRIPTION
The ADSP-2148x SHARC® processors are members of the
SIMD SHARC family of DSPs that feature Analog Devices’
Super Harvard Architecture. The processors are source code
compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x,
ADSP-2146x, ADSP-2147x and ADSP-2116x DSPs, as well as
with first generation ADSP-2106x SHARC processors in SISD
(single-instruction, single-data) mode. The ADSP-2148x pro-
cessors are 32-bit/40-bit floating point processors optimized for
high performance audio applications with large on-chip SRAM,
multiple internal buses to eliminate I/O bottlenecks, and an
innovative digital applications interface (DAI).
Table 1 shows performance benchmarks for the ADSP-2148x
processors. Table 2 shows the features of the individual product
offerings.
Table 1. Processor Benchmarks
Benchmark Algorithm
Speed
(at 400 MHz)
1024 Point Complex FFT
(Radix 4, with Reversal)
FIR Filter (per Tap)1
IIR Filter (per Biquad)1
23 μs
1.25 ns
5 ns
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
11.25 ns
20 ns
Divide (y/×)
7.5 ns
Inverse Square Root
11.25 ns
1 Assumes two files in multichannel SIMD mode
Speed
(at 450 MHz)
20.44 μs
1.1 ns
4.43 ns
10.0 ns
17.78 ns
6.67 ns
10.0 ns
Table 2. ADSP-2148x Family Features
Feature
ADSP-21483 ADSP-21486 ADSP-21487 ADSP-21488 ADSP-21489
Maximum Instruction Rate
RAM
400 MHz
3 Mbits
400 MHz
450 MHz
5 Mbits
400 MHz
2/3 Mbits1
450 MHz
5 Mbits
ROM
Audio Decoders in ROM2
4 Mbits
Yes
No
No
Pulse-Width Modulation
4 Units (3 Units on 100-Lead Packages)
DTCP Hardware Accelerator
External Port Interface (SDRAM, AMI)3
Yes (16-bit)
Contact Analog Devices
AMI Only
Yes (16-bit)
Serial Ports
8
Direct DMA from SPORTs to External Port
(External Memory)
Yes
FIR, IIR, FFT Accelerator
Yes
Watchdog Timer
Yes (176-Lead Package Only)
MediaLB Interface
Automotive Models Only
IDP/PDAP
Yes
UART
1
DAI (SRU)/DPI (SRU2)
Yes
S/PDIF Transceiver
Yes
SPI Yes
TWI
SRC Performance4
1
–128 dB
Thermal Diode
Yes
VISA Support
Package3
176-Lead LQFP EPAD
100-Lead LQFP EPAD
Yes
176-Lead LQFP
EPAD
176-Lead LQFP EPAD
100-Lead LQFP EPAD5
1 See Ordering Guide on Page 66.
2 ROM is factory programmed with latest multichannel audio decoding and post-processing algorithms from Dolby® Labs and DTS®. Decoder/post-processor algorithm
combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information.
3 The 100-lead packages do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function
Descriptions on Page 14. The ADSP-21486 processor in the 176-lead package also does not contain a SDRAM controller. For more information, see 176-Lead LQFP_EP
Lead Assignment on page 60.
4 Some models have –140 dB performance. For more information, see Ordering Guide on page 66.
5 Only available up to 400 MHz. See Ordering Guide on Page 66 for details.
Rev. C | Page 3 of 68 | June 2015



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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
The diagram on Page 1 shows the two clock domains that make
up the ADSP-2148x processors. The core clock domain contains
the following features:
• Two processing elements (PEx, PEy), each of which com-
prises an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting 2x64-bit data
transfers between memory and the core at every core pro-
cessor cycle
• One periodic interval timer with pinout
• On-chip SRAM (5 Mbit) and mask-programmable ROM
(4 Mbit)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break-
points which allows flexible exception handling.
The block diagram of the ADSP-2148x on Page 1 also shows the
peripheral clock domain (also known as the I/O processor)
which contains the following features:
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
• Peripheral and external port buses for core connection
• External port with an AMI and SDRAM controller
• 4 units for PWM control
• 1 memory-to-memory (MTM) unit for internal-to-internal
memory transfers
• Digital applications interface that includes four precision
clock generators (PCG), an input data port (IDP/PDAP)
for serial and parallel interconnects, an S/PDIF
receiver/transmitter, four asynchronous sample rate con-
verters, eight serial ports, and a flexible signal routing unit
(DAI SRU).
• Digital peripheral interface that includes two timers, a
2-wire interface (TWI), one UART, two serial peripheral
interfaces (SPI), 2 precision clock generators (PCG), pulse
width modulation (PWM), and a flexible signal routing
unit (DPI SRU2).
As shown in the SHARC core block diagram on Page 5, the
processor uses two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. With its SIMD computational hard-
ware, the processors can perform 2.7 GFLOPS running at
450 MHz.
FAMILY CORE ARCHITECTURE
The ADSP-2148x is code compatible at the assembly level with
the ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x,
ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first
generation ADSP-2106x SHARC processors. The ADSP-2148x
shares architectural features with the ADSP-2126x, ADSP-
2136x, ADSP-2137x, ADSP-2146x and ADSP-2116x SIMD
SHARC processors, as shown in Figure 2 and detailed in the fol-
lowing sections.
SIMD Computational Engine
The ADSP-2148x contains two computational processing ele-
ments that operate as a single-instruction, multiple-data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter, and reg-
ister file. PEx is always active, and PEy may be enabled by
setting the PEYEN mode bit in the MODE1 register. SIMD
mode allows the processor to execute the same instruction in
both processing elements, but each processing element operates
on different data. This architecture is efficient at executing math
intensive DSP algorithms.
SIMD mode also affects the way data is transferred between
memory and the processing elements because twice the data
bandwidth is required to sustain computational operation in the
processing elements. Therefore, entering SIMD mode also dou-
bles the bandwidth between memory and the processing
elements. When using the DAGs to transfer data in SIMD
mode, two data values are transferred with each memory or reg-
ister file access.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle and are arranged in parallel, maximizing
computational throughput. Single multifunction instructions
execute parallel ALU and multiplier operations. In SIMD mode,
the parallel ALU and multiplier operations occur in both pro-
cessing elements. These computation units support IEEE 32-bit
single-precision floating-point, 40-bit extended precision float-
ing-point, and 32-bit fixed-point data formats.
Timer
The processor contains a core timer that can generate periodic
software interrupts. The core timer can be configured to use
FLAG3 as a timer expired signal.
Data Register File
Each processing element contains a general-purpose data regis-
ter file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register (16 primary, 16 secondary) register files,
combined with the processor’s enhanced Harvard architecture,
allow unconstrained data flow between computation units and
internal memory. The registers in PEX are referred to as
R0–R15 and in PEY as S0–S15.
Context Switch
Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result registers all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.
Rev. C | Page 4 of 68 | June 2015



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