The ADSP-21367/ADSP-21368/ADSP-21369 SHARC® proces-
sors are members of the SIMD SHARC family of DSPs that
feature Analog Devices’ Super Harvard Architecture. These pro-
cessors are source code-compatible with the ADSP-2126x and
ADSP-2116x DSPs as well as with first generation ADSP-2106x
SHARC processors in SISD (single-instruction, single-data)
mode. The processors are 32-bit/40-bit floating-point proces-
sors optimized for high performance automotive audio
applications with its large on-chip SRAM, mask programmable
ROM, multiple internal buses to eliminate I/O bottlenecks, and
an innovative digital applications interface (DAI).
As shown in the functional block diagram on Page 1, the
processors use two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the ADSP-21367/ADSP-21368/
ADSP-21369 processors achieve an instruction cycle time of up
to 2.5 ns at 400 MHz. With its SIMD computational hardware,
the processors can perform 2.4 GFLOPS running at 400 MHz.
Table 1 shows performance benchmarks for these devices.
Table 1. Processor Benchmarks (at 400 MHz)
(at 400 MHz)
1024 Point Complex FFT (Radix 4, with reversal) 23.2 s
FIR Filter (per tap)1
IIR Filter (per biquad)1
Matrix Multiply (pipelined)
[3×3] × [3×1]
[4×4] × [4×1]
Inverse Square Root
1 Assumes two files in multichannel SIMD mode.
Table 2. ADSP-2136x Family Features1
Audio Decoders in ROM
SDRAM Memory Bus Width
Table 2. ADSP-2136x Family Features1 (Continued)
AMI Interface Bus Width
1 W = Automotive grade product. See Automotive Products on Page 61 for more
2 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,
DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass
management, delay, speaker equalization, graphic equalization, and more.
Decoder/post-processor algorithm combination support varies depending upon
the chip version and the system configurations. Please visit www.analog.com for
The diagram on Page 1 shows the two clock domains that make
up the ADSP-21367/ADSP-21368/ADSP-21369 processors. The
core clock domain contains the following features.
• Two processing elements (PEx, PEy), each of which com-
prises an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting 2x64-bit data
transfers between memory and the core at every core pro-
• One periodic interval timer with pinout
• On-chip SRAM (2M bit)
• On-chip mask-programmable ROM (6M bit)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break-
points which allows flexible exception handling.
Rev. F | Page 3 of 64 | October 2013