ADSP-21368 Datasheet PDF - Analog Devices

www.Datasheet-PDF.com

ADSP-21368
Analog Devices

Part Number ADSP-21368
Description SHARC Processor
Page 30 Pages


ADSP-21368 datasheet pdf
Download PDF
ADSP-21368 pdf
View PDF for Mobile

No Preview Available !

SHARC Processor
ADSP-21367/ADSP-21368/ADSP-21369
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—2M bits of on-chip SRAM and 6M bits of
on-chip mask programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21367/ADSP-21368/ADSP-21369 are available
with a 400 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, 8-channel asynchronous
sample rate converter, precision clock generators, and
more. For complete ordering information, see Ordering
Guide on Page 61.
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter
4 independent asynchronous sample rate converters (SRC)
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Available in 256-ball BGA_ED and 208-lead LQFP_EP
packages
SIMD Core
Instruction
Cache
5 stage
Sequencer
DAG1/2
Timer
PEx PEy
FLAGx/IRQx/
TMREXP
JTAG
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
DMD
64-BIT
S
DMD 64-BIT
PMD
64-BIT
Core Bus
Cross Bar
PERIPHERAL BUS
32-BIT
PMD 64-BIT
EPD BUS 32-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D
64-BIT
IOD1
32-BIT
PERIPHERAL BUS
IOD0 BUS
MTM
EP
CORE PCG
FLAGS C-D
TIMER
2-0
TWI
SPI/B
UART
1-0
S/PDIF PCG
Tx/Rx A-D
ASRC IDP/ SPORT
3-0 PDAP 7-0
7-0
CORE PWM
FLAGS 3-0
AMI SDRAM
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
External Port Pin MUX
Peripherals
External
Port
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com



No Preview Available !

ADSP-21367/ADSP-21368/ADSP-21369
TABLE OF CONTENTS
Summary ............................................................... 1
Dedicated Audio Components ................................. 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 4
Family Peripheral Architecture ................................ 7
I/O Processor Features ......................................... 10
System Design .................................................... 10
Development Tools ............................................. 11
Additional Information ........................................ 12
Related Signal Chains .......................................... 12
Pin Function Descriptions ....................................... 13
Specifications ........................................................ 16
Operating Conditions .......................................... 16
Electrical Characteristics ....................................... 17
Package Information ........................................... 18
ESD Caution ...................................................... 18
Maximum Power Dissipation ................................. 18
Absolute Maximum Ratings ................................... 18
Timing Specifications ........................................... 18
Output Drive Currents ......................................... 51
Test Conditions .................................................. 51
Capacitive Loading .............................................. 51
Thermal Characteristics ........................................ 53
256-Ball BGA_ED Pinout ......................................... 54
208-Lead LQFP_EP Pinout ....................................... 57
Package Dimensions ............................................... 59
Surface-Mount Design .......................................... 60
Automotive Products .............................................. 61
Ordering Guide ..................................................... 61
REVISION HISTORY
10/13—Rev. E to Rev. F
Updated Development Tools ..................................... 11
Added Related Signal Chains ..................................... 12
Corrected EMU pin type from O/T(pu) to O(O/D, pu) in
Pin Function Descriptions ........................................ 13
Corrected Junction Temperature 256-Ball BGA Min Value at
ambient temperature (–40°C to +85C) from 0 to –40 in
Operating Conditions .............................................. 16
Added 400 MHz Min and Max values for Junction Temperature
208-Lead LQFP_EP at ambient temperature 0°C to +70C in
Operating Conditions .............................................. 16
Added footnote 2 to Table 24 in Memory Read .............. 30
Changed Max values in Table 34 in Pulse-Width Modulation
Generators ............................................................ 41
Updated timing parameters in Table 40 and in Figure 36 in
SPI Interface—Master .............................................. 48
Updated Figure 37 in SPI Interface—Slave .................... 49
Changes to Ordering Guide ....................................... 61
To view product/process change notifications (PCNs) related to
this data sheet revision, please visit the processor’s product page
on the www.analog.com website and use the View PCN link.
Rev. F | Page 2 of 64 | October 2013



No Preview Available !

ADSP-21367/ADSP-21368/ADSP-21369
GENERAL DESCRIPTION
The ADSP-21367/ADSP-21368/ADSP-21369 SHARC® proces-
sors are members of the SIMD SHARC family of DSPs that
feature Analog Devices’ Super Harvard Architecture. These pro-
cessors are source code-compatible with the ADSP-2126x and
ADSP-2116x DSPs as well as with first generation ADSP-2106x
SHARC processors in SISD (single-instruction, single-data)
mode. The processors are 32-bit/40-bit floating-point proces-
sors optimized for high performance automotive audio
applications with its large on-chip SRAM, mask programmable
ROM, multiple internal buses to eliminate I/O bottlenecks, and
an innovative digital applications interface (DAI).
As shown in the functional block diagram on Page 1, the
processors use two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the ADSP-21367/ADSP-21368/
ADSP-21369 processors achieve an instruction cycle time of up
to 2.5 ns at 400 MHz. With its SIMD computational hardware,
the processors can perform 2.4 GFLOPS running at 400 MHz.
Table 1 shows performance benchmarks for these devices.
Table 1. Processor Benchmarks (at 400 MHz)
Benchmark Algorithm
Speed
(at 400 MHz)
1024 Point Complex FFT (Radix 4, with reversal) 23.2 s
FIR Filter (per tap)1
1.25 ns
IIR Filter (per biquad)1
5.0 ns
Matrix Multiply (pipelined)
[3×3] × [3×1]
11.25 ns
[4×4] × [4×1]
20.0 ns
Divide (y/x)
8.75 ns
Inverse Square Root
13.5 ns
1 Assumes two files in multichannel SIMD mode.
Table 2. ADSP-2136x Family Features1
Feature
Frequency
RAM
ROM2
Audio Decoders in ROM
Pulse-Width Modulation
S/PDIF
SDRAM Memory Bus Width
400 MHz
2M bits
6M bits
Yes
Yes
Yes
32/16 bits
Table 2. ADSP-2136x Family Features1 (Continued)
Feature
Serial Ports
8
IDP Yes
DAI Yes
UART
2
DAI Yes
DPI Yes
S/PDIF Transceiver
1
AMI Interface Bus Width
32/16/8 bits
SPI 2
TWI Yes
SRC Performance
128 dB
Package
256 Ball-
BGA,
208-Lead
LQFP_EP
256 Ball-
BGA
256 Ball-
BGA,
208-Lead
LQFP_EP
1 W = Automotive grade product. See Automotive Products on Page 61 for more
information.
2 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,
DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass
management, delay, speaker equalization, graphic equalization, and more.
Decoder/post-processor algorithm combination support varies depending upon
the chip version and the system configurations. Please visit www.analog.com for
complete information.
The diagram on Page 1 shows the two clock domains that make
up the ADSP-21367/ADSP-21368/ADSP-21369 processors. The
core clock domain contains the following features.
• Two processing elements (PEx, PEy), each of which com-
prises an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting 2x64-bit data
transfers between memory and the core at every core pro-
cessor cycle
• One periodic interval timer with pinout
• On-chip SRAM (2M bit)
• On-chip mask-programmable ROM (6M bit)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break-
points which allows flexible exception handling.
Rev. F | Page 3 of 64 | October 2013



No Preview Available !

ADSP-21367/ADSP-21368/ADSP-21369
The block diagram of the ADSP-21368 on Page 1 also shows the
peripheral clock domain (also known as the I/O processor) and
contains the following features:
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
• Peripheral and external port buses for core connection
• External port with an AMI and SDRAM controller
• 4 units for PWM control
• 1 MTM unit for internal-to-internal memory transfers
• Digital applications interface that includes four precision
clock generators (PCG), a input data port (IDP) for serial
and parallel interconnect, an S/PDIF receiver/transmitter,
four asynchronous sample rate converters, eight serial
ports, a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes three timers, a 2-
wire interface, two UARTs, two serial peripheral interfaces
(SPI), 2 precision clock generators (PCG) and a flexible sig-
nal routing unit (DPI SRU).
SHARC FAMILY CORE ARCHITECTURE
The ADSP-21367/ADSP-21368/ADSP-21369 are code compati-
ble at the assembly level with the ADSP-2126x, ADSP-21160,
and ADSP-21161, and with the first generation ADSP-2106x
SHARC processors. The ADSP-21367/ADSP-21368/
ADSP-21369 processors share architectural features with the
ADSP-2126x and ADSP-2116x SIMD SHARC processors, as
shown in Figure 2 and detailed in the following sections.
S
SIMD Core
DMD/PMD 64
DAG1
16x32
DAG2
16x32
JTAG FLAG TIMER INTERRUPT CACHE
5 STAGE
PROGRAM SEQUENCER
PM ADDRESS 24
PM DATA 48
PM ADDRESS 32
DM ADDRESS 32
PM DATA 64
DM DATA 64
SYSTEM
I/F
USTAT
4x32-BIT
PX
64-BIT
MULTIPLIER SHIFTER ALU
RF
Rx/Fx
PEx
16x40-BIT
DATA
SWAP
RF
Sx/SFx
PEy
16x40-BIT
ALU
SHIFTER MULTIPLIER
MRF
80-BIT
MRB
80-BIT
ASTATx
STYKx
ASTATy
STYKy
MSB
80-BIT
MSF
80-BIT
Figure 2. SHARC Core Block Diagram
Rev. F | Page 4 of 64 | October 2013



ADSP-21368 datasheet pdf
Download PDF
ADSP-21368 pdf
View PDF for Mobile


Related : Start with ADSP-2136 Part Numbers by
ADSP-21362 (ADSP-21362 - ADSP-21366) SHARC Processor ADSP-21362
Analog Devices
ADSP-21362 pdf
ADSP-21363 (ADSP-21362 - ADSP-21366) SHARC Processor ADSP-21363
Analog Devices
ADSP-21363 pdf
ADSP-21364 (ADSP-21362 - ADSP-21366) SHARC Processor ADSP-21364
Analog Devices
ADSP-21364 pdf
ADSP-21365 (ADSP-21362 - ADSP-21366) SHARC Processor ADSP-21365
Analog Devices
ADSP-21365 pdf
ADSP-21366 (ADSP-21362 - ADSP-21366) SHARC Processor ADSP-21366
Analog Devices
ADSP-21366 pdf
ADSP-21367 SHARC Processor ADSP-21367
Analog Devices
ADSP-21367 pdf
ADSP-21368 SHARC Processor ADSP-21368
Analog Devices
ADSP-21368 pdf
ADSP-21369 SHARC Processors ADSP-21369
Analog Devices
ADSP-21369 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact