ADRF6801 Datasheet PDF - Analog Devices

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ADRF6801
Analog Devices

Part Number ADRF6801
Description 750 MHz to 1150 MHz Quadrature Demodulator
Page 30 Pages


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750 MHz to 1150 MHz Quadrature
Demodulator with Fractional-N PLL and VCO
ADRF6801
FEATURES
IQ demodulator with integrated fractional-N PLL
LO frequency range: 750 MHz to 1150 MHz
Input P1dB: 12.5 dBm
Input IP3: 25 dBm
Noise figure (DSB): 14.3 dB
Voltage conversion gain: 5.1 dB
Quadrature demodulation accuracy
Phase accuracy: 0.3°
Amplitude accuracy: 0.05 dB
Baseband demodulation: 275 MHz, 3 dB bandwidth
SPI serial interface for PLL programming
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
QAM/QPSK RF/IF demodulators
Cellular W-CDMA/CDMA/CDMA2000
Microwave point-to-(multi)point radios
Broadband wireless and WiMAX
GENERAL DESCRIPTION
The ADRF6801 is a high dynamic range IQ demodulator with
integrated PLL and VCO. The fractional-N PLL/synthesizer
generates a frequency in the range of 3.0 GHz to 4.6 GHz. A
divide-by-4 quadrature divider divides the output frequency of
the VCO down to the required local oscillator (LO) frequency
to drive the mixers in quadrature. Additionally, an output buffer
can be enabled that generates an fVCO/2 signal for external use.
The PLL reference input is supported from 10 MHz to 160 MHz.
The phase detector output controls a charge pump whose output
is integrated in an off-chip loop filter. The loop filter output is
then applied to an integrated VCO.
The IQ demodulator mixes the differential RF input with the
complex LO derived from the quadrature divider. The differential
I and Q output paths have excellent quadrature accuracy and
can handle baseband signaling or complex IF up to 120 MHz.
The ADRF6801 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, exposed-paddle,
RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is
specified over the −40°C to +85°C temperature range.
LON 37
LOP 38
GND 11
DATA 12
CLK 13
LE 14
GND 15
REFIN 6
GND 7
MUXOUT 8
FUNCTIONAL BLOCK DIAGRAM
GND
35
VCCLO VCCLO
34 17
LOSEL
36
BUFFER
CTRL
BUFFER
IBBP
33
ADRF6801
SPI
INTERFACE
×2
MUX
÷2
÷4
FRACTION
REG
MODULUS
INTEGER
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
BUFFER
PRESCALER
÷2
MUX
DIVIDER
÷1
OR
÷2
VCO
CORE
QUAD
÷2
TEMP
SENSOR
3.3V LDO
+
PHASE
FREQUENCY
DETECTOR
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
2.5V LDO
VCO LDO
IBBN GND
32 31
30 GND
29 VCCBB
28 GND
27 VCCRF
26 RFIN
25 GNDRF
24 GND
23 GND
22 VCCBB
21 GND
1 2 10
VCC1 DECL3 VCC2
16
GND
34
5
CPOUT GND RSET
Figure 1.
9
DECL2
39
VTUNE
40
DECL1
18 19 20
QBBP QBBN GND
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Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.



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ADRF6801
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
Timing Characteristics ................................................................ 5 
Absolute Maximum Ratings............................................................ 6 
ESD Caution.................................................................................. 6 
Pin Configuration and Function Descriptions............................. 7 
Typical Performance Characteristics ............................................. 9 
Synthesizer/PLL .......................................................................... 12 
Complementary Cumulative Distribution Functions (CCDF)
....................................................................................................... 13 
Circuit Description......................................................................... 14 
LO Quadrature Drive................................................................. 14 
V-to-I Converter......................................................................... 14 
Mixers .......................................................................................... 14 
Emitter Follower Buffers ........................................................... 14 
REVISION HISTORY
1/11—Revision 0: Initial Version
Bias Circuitry .............................................................................. 14 
Register Structure....................................................................... 14 
Applications Information .............................................................. 21 
Basic Connections...................................................................... 21 
Supply Connections ................................................................... 21 
Synthesizer Connections ........................................................... 21 
I/Q Output Connections ........................................................... 22 
RF Input Connections ............................................................... 22 
Charge Pump/VTUNE Connections ...................................... 22 
LO Select Interface ..................................................................... 22 
External LO Interface ................................................................ 22 
Setting the Frequency of the PLL ............................................. 22 
Register Programming............................................................... 22 
EVM Measurements .................................................................. 23 
Evaluation Board Layout and Thermal Grounding................... 24 
ADRF6801 Software .................................................................. 28 
Characterization Setups................................................................. 30 
Outline Dimensions ....................................................................... 34 
Ordering Guide .......................................................................... 34 
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Rev. 0 | Page 2 of 36



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ADRF6801
SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25°C; fREF = 26 MHz, fLO = 900 MHz, fBB = 4.5 MHz, RLOAD = 450 Ω differential, all register and PLL
settings use the recommended values shown in the Register Structure section, unless otherwise noted.
Table 1.
Parameter
RF INPUT AT 900 MHz
Internal LO Frequency Range
Input Return Loss
Input P1dB
Second-Order Input Intercept (IIP2)
Third-Order Input Intercept (IIP3)
Noise Figure
LO-to-RF Leakage
I/Q BASEBAND OUTPUTS
Voltage Conversion Gain
Demodulation Bandwidth
Quadrature Phase Error
I/Q Amplitude Imbalance
Output DC Offset (Differential)
Output Common-Mode Voltage
Gain Flatness
Maximum Output Swing
Maximum Output Current
LO INPUT/OUTPUT
Output Level
Input Level
Input Impedance
VCO Operating Frequency
SYNTHESIZER SPECIFICATIONS
Channel Spacing
PLL Bandwidth
SPURS
Reference Spurs
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Test Conditions/Comments
RFIN pins
With VCO amplitude = 63 (R6 [DB15 to DB10])
With VCO amplitude = 24 (R6 [DB15 to DB10])
Measured at 900 MHz
−5 dBm each tone
−5 dBm each tone
Double sideband from RF to either I or Q output
With a −10 dBm interferer 5 MHz away
At 1×LO frequency, 50 Ω termination at the RF port
IBBP, IBBN, QBBP, QBBN pins
450 Ω differential load across IBBP, IBBN (or QBBP, QBBN)
1 V p-p signal 3 dB bandwidth
Any 5 MHz (<100 MHz)
Differential 450 Ω load
Differential 200 Ω load
Each pin
LOP, LON
Into a differential 50 Ω load, LO buffer enabled (LO
frequency = 900 MHz, output frequency = 1800 MHz)
Externally applied 2×LO, PLL disabled
Externally applied 2×LO, PLL disabled
With VCO amplitude = 63 (R6 [DB15 to DB10])
With VCO amplitude = 24 (R6 [DB15 to DB10])
All synthesizer specifications measured with
recommended settings provided in Figure 33 through
Figure 39
fPFD = 26 MHz; modulus = 2047
Can be adjusted with off-chip loop filter component
values and RSET
fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured
at BB outputs with fBB = 50 MHz
fREF = 26 MHz, fPFD = 26 MHz
fPFD/2
fPFD × 2
fPFD × 3
Min Typ
750
750
<−20
12.5
>65
25
14.3
18.9
−75
5.1
275
0.3
0.05
±5
VPOS − 2.4
0.2
4
2.4
12
−2.5
3000
3000
0
50
25
130
−91.6
−107.8
−89.1
−94.2
Max Unit
1125
1150
MHz
MHz
dB
dBm
dBm
dBm
dB
dB
dBm
dB
MHz
Degrees
dB
mV
V
dB p-p
V p-p
V p-p
mA p-p
dBm
4500
4600
dBm
Ω
MHz
MHz
kHz
kHz
dBc
dBc
dBc
dBc
Rev. 0 | Page 3 of 36



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ADRF6801
Parameter
Test Conditions/Comments
Min Typ
PHASE NOISE (USING 130 kHz LOOP FILTER) fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured
at BB outputs with fBB = 50 MHz
1 kHz offset
−99.5
10 kHz offset
−107.8
100 kHz offset
−106.6
500 kHz offset
−126.7
1 MHz offset
−131.7
5 MHz offset
−143.5
10 MHz offset
−150.5
Integrated Phase Noise
1 kHz to 10 MHz integration bandwidth
0.16
PHASE NOISE (USING 2.5 kHz LOOP FILTER) fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured
at BB outputs with fBB = 50 MHz
1 kHz offset
−71.3
10 kHz offset
−88.3
100 kHz offset
−114.1
500 kHz offset
−129.5
1 MHz offset
−138.6
5 MHz offset
−150.2
10 MHz offset
−150.3
PLL FIGURE OF MERIT (FOM)
Measured with fREF = 26 MHz, fPFD = 26 MHz
−215.4
Measured with fREF = 104 MHz, fPFD = 26 MHz
−220.9
Phase Detector Frequency
20 26
REFERENCE CHARACTERISTICS
REFIN, MUXOUT pins
REFIN Input Frequency
Usable range
10
REFIN Input Capacitance
4
MUXOUT Output Level
VOL (lock detect output selected)
VOH (lock detect output selected)
2.7
REFOUT Duty Cycle
50
CHARGE PUMP
Pump Current
500
Output Compliance Range
1
LOGIC INPUTS
CLK, DATA, LE pins
Input High Voltage, VINH
1.4
Input Low Voltage, VINL
0
Input Current, IINH/IINL
0.1
Input Capacitance, CIN
5
POWER SUPPLIES
VCC1, VCC2, VCCLO, VCCBB, VCCRF pins
Voltage Range (5 V)
4.75 5
Supply Current (5 V)
Normal Rx mode, internal LO
262
Rx mode, internal LO with LO buffer enabled
288
Rx mode, using external LO input (internal VCO, PLL shut
down)
157
Supply Current (5 V)
Power-down mode
20
Max Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz/Hz
dBc/Hz/Hz
40 MHz
160 MHz
pF
0.25 V
V
%
μA
2.8 V
3.3 V
0.7 V
μA
pF
5.25 V
mA
mA
mA
mA
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Rev. 0 | Page 4 of 36



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