ADF7241 Datasheet PDF - Analog Devices

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ADF7241
Analog Devices

Part Number ADF7241
Description Low Power IEEE 802.15.4 Zero-IF 2.4 GHz Transceiver IC
Page 30 Pages


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Low Power IEEE 802.15.4 Zero-IF 2.4 GHz
Transceiver IC
ADF7241
FEATURES
Frequency range (global ISM band)
2400 MHz to 2483.5 MHz
IEEE 802.15.4-2006-compatible (250 kbps)
Low power consumption
19 mA (typical) in receive mode
21.5 mA (typical) in transmit mode (PO = 3 dBm)
1.7 μA, 32 kHz crystal oscillator wake-up mode
High sensitivity
−95 dBm at 250 kbps
Programmable output power
−20 dBm to +4.8 dBm in 2 dB steps
Integrated voltage regulators
1.8 V to 3.6 V input voltage range
Excellent receiver selectivity and blocking resilience
Zero-IF architecture
Complies with EN300 440 Class 2, EN300 328, FCC CFR47
Part 15, ARIB STD-T66
Digital RSSI measurement
Fast automatic VCO calibration
Automatic RF synthesizer bandwidth optimization
On-chip low power processor performs
Radio control
Packet management
Packet management support
Insertion/detection of preamble address/SFD/FCS
IEEEE 802.15.4-2006 frame filtering
IEEEE 802.15.4-2006 CSMA/CA unslotted modes
Flexible 256-byte transmit/receive data buffer
SPORT mode
Flexible multiple RF port interface
External PA/LNA support hardware
Switched antenna diversity support
Wake-up timer
Very few external components
Integrated PLL loop filter, receive/transmit switch, battery
monitor, temperature sensor, 32 kHz RC and crystal
oscillators
Flexible SPI control interface with block read/write access
Small form factor 5 mm × 5 mm 32-lead LFCSP package
APPLICATIONS
Wireless sensor networks
Automatic meter reading/smart metering
Industrial wireless control
Healthcare
Wireless audio/video
Consumer electronics
ZigBee
ADF7241
LNA1
LNA2
FUNCTIONAL BLOCK DIAGRAM
DAC
ADC
ADC
DAC
DSSS
DEMOD
AGC
OCL
CDR
8-BIT
PROCESSOR
RADIO
CONTROLLER
PACKET
MANAGER
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PA
LDO × 4
FRACTIONAL-N
RF SYNTHESIZER
PRE-EMPHASIS FILTER
WAKE-UP CTRL
BIAS
BATTERY TEMPERATURE
MONITOR
SENSOR
26MHz
OSC
32kHz
RC
OSC
32kHz
XTAL
OSC
4kB
PROGRAM
ROM
2kB
PROGRAM
RAM
256-BYTE
PACKET
RAM
64-BYTE
BBRAM
256-BYTE
MCR
SPI
GPIO
SPORT
IRQ
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.



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ADF7241
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
General Description ......................................................................... 3 
Specifications..................................................................................... 5 
General Specifications ................................................................. 5 
RF Frequency Synthesizer Specifications.................................. 5 
Transmitter Specifications........................................................... 6 
Receiver Specifications ................................................................ 6 
Auxiliary Specifications ............................................................... 8 
Current Consumption Specifications ........................................ 9 
Timing and Digital Specifications.............................................. 9 
Timing Diagrams........................................................................ 11 
Absolute Maximum Ratings.......................................................... 15 
ESD Caution................................................................................ 15 
Pin Configuration and Function Descriptions........................... 16 
Typical Performance Characteristics ........................................... 18 
Terminology .................................................................................... 22 
Radio Controller ............................................................................. 23 
Sleep Modes................................................................................. 25 
RF Frequency Synthesizer ............................................................. 26 
RF Frequency Synthesizer Calibration .................................... 26 
RF Frequency Synthesizer Bandwidth..................................... 27 
RF Channel Frequency Programming..................................... 27 
Reference Crystal Oscillator ..................................................... 27 
Transmitter ...................................................................................... 28 
Transmit Operating Modes ....................................................... 28 
IEEE 802.15.4 Automatic RX-To-TX Turnaround Mode..... 30 
Power Amplifier.......................................................................... 30 
Receiver............................................................................................ 33 
Receive Operation ...................................................................... 33 
Receiver Calibration................................................................... 33 
Receive Timing and Control ....................................................... 35 
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Clear Channel Assessment (CCA) ........................................... 36 
Link Quality Indication (LQI) .................................................. 36 
Automatic TX-to-RX Turnaround Mode ............................... 37 
IEEE 802.15.4 Frame Filtering, Automatic Acknowledge, and
Automatic CSMA/CA................................................................ 37 
Receiver Radio Blocks ............................................................... 39 
SPORT Interface ............................................................................. 40 
SPORT Mode .............................................................................. 40 
Device Configuration .................................................................... 41 
Configuration Values ................................................................. 41 
RF Port Configurations/Antenna Diversity................................ 42 
Auxillary Functions........................................................................ 43 
Temperture Sensor ..................................................................... 43 
Battery Monitor .......................................................................... 43 
Wake-Up Controller (WUC).................................................... 43 
Transmit Test Modes.................................................................. 44 
Serial Peripheral interface (SPI) ................................................... 45 
General Characteristics ............................................................. 45 
Command Access....................................................................... 45 
Status Word ................................................................................. 45 
Memory Map .................................................................................. 47 
BBRAM........................................................................................ 47 
Modem Configuration RAM (MCR) ...................................... 47 
Program ROM ............................................................................ 47 
Program RAM ............................................................................ 47 
Packet RAM ................................................................................ 47 
Memory Access............................................................................... 49 
Writing to the ADF7241............................................................ 50 
Reading from the ADF7241...................................................... 50 
Downloadable Firmware Modules............................................... 53 
Interrupt Controller ....................................................................... 54 
Configuration ............................................................................. 54 
Description of Interrupt Sources ............................................. 55 
Applications Circuits...................................................................... 56 
Register Map ................................................................................... 60 
Outline Dimensions ....................................................................... 71 
Ordering Guide .......................................................................... 71 
REVISION HISTORY
1/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 72



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GENERAL DESCRIPTION
The ADF7241 is a highly integrated, low power, and high perfor-
mance transceiver for operation in the global 2.4 GHz ISM band. It
is designed with emphasis on flexibility, robustness, ease of use,
and low current consumption. The IC supports the IEEE 802.15.4-
2006 2.4 GHz PHY requirements in both packet and data
streaming modes. With a minimum number of external compo-
nents, it achieves compliance with the FCC CFR47 Part 15,
ETSI EN 300 440 (Equipment Class 2), ETSI EN 300 328
(FHSS, DR > 250 kbps), and ARIB STD T-66 standards.
The ADF7241 complies with the IEEE 802.15.4-2006 2.4 GHz
PHY requirements with a fixed data rate of 250 kbps and DSSS-
OQPSK modulation. The transmitter path of the ADF7241 is
based on a direct closed-loop VCO modulation scheme using a
low noise fractional-N RF frequency synthesizer. The
automatically calibrated VCO operates at twice the fundamental
frequency to reduce spurious emissions and avoid PA pulling
effects. The bandwidth of the RF frequency synthesizer is
automatically optimized for transmit and receive operations to
achieve best phase noise, modulation quality, and synthesizer
settling time performance. The transmitter output power is
programmable from −20 dBm to +4 dBm with automatic PA
ramping to meet transient spurious specifications. An
integrated biasing and control circuit is available in the IC to
significantly simplify the interface to external PAs.
The receive path is based on a zero-IF architecture enabling very
high blocking resilience and selectivity performance, which are
critical performance metrics in interference dominated environ-
ments such as the 2.4 GHz band. In addition, the architecture
does not suffer from any degradation of blocker rejection in the
image channel, which is typically found in low IF receivers. The
IC can operate with a supply voltage between 1.8 V and 3.6 V with
very low power consumption in receive and transmit modes while
maintaining its excellent RF performance, making it especially
suitable for battery-powered systems.
The ADF7241 features a flexible dual-port RF interface that can
be used with an external LNA and/or PA in addition to support-
ing switched antenna diversity.
The ADF7241 incorporates a very low power custom 8-bit
processor that supports a number of transceiver management
functions. These functions are handled by the two main mod-
ules of the processor: the radio controller and the packet manager.
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ADF7241
The radio controller manages the state of the IC in various
operating modes and configurations. The host MCU can use
single byte commands to interface to the radio controller. In
transmit mode, the packet manager can be configured to add
preamble and SFD to the payload data stored in the on-chip
packet RAM. In receive mode, the packet manager can detect
and generate an interrupt to the MCU upon receiving a valid SFD,
and store the received data payload in the packet RAM. A total
of 256 bytes of transmit and receive packet RAM space is
provided to decouple the over-the-air data rate from the host
MCU processing speed. Thus, the ADF7241 packet manager
eases the processing burden on the host MCU and saves the
overall system power consumption.
In addition, for applications that require data streaming, a
synchronous bidirectional serial port (SPORT) provides bit-
level input/output data, and has been designed to directly
interface to a wide range of DSPs, such as ADSP-21xx, SHARC®,
TigerSHARC®, and Blackfin®. The SPORT interface can option-
ally be used.
The processor also permits the download and execution of a set
of firmware modules, which include IEEE 802.15.4 automatic
modes, such as node address filtering, as well as unslotted
CSMA/CA. Execution code for these firmware modules is
available from Analog Devices, Inc.
To further optimize the system power consumption, the ADF7241
features an integrated low power 32 kHz RC wake-up oscillator,
which is calibrated from the 26 MHz crystal oscillator while the
transceiver is active. Alternatively, an integrated 32 kHz crystal
oscillator can be used as a wake-up timer for applications
requiring very accurate wake-up timing. A battery backed-up
RAM (BBRAM) is available on the IC where IEEE 802.15.4-
2006 network node addresses can be retained when the IC is in
the sleep state.
The ADF7241 also features a very flexible interrupt controller,
which provides MAC-level and PHY-level interrupts to the host
MCU. The IC is equipped with a SPI interface, which allows
burst mode data transfer for high data throughput efficiency.
The IC also integrates a temperature sensor with digital read-
back and a battery monitor.
Rev. 0 | Page 3 of 72



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ADF7241
RFIO1P
RFIO1N
RFIO2P
RFIO2N
ADF7241
LNA1
LNA2
DAC
ADC
ADC
DAC
DSSS
DEMOD
AGC
OCL
CDR
8-BIT
PROCESSOR
RADIO
CONTROLLER
PACKET
MANAGER
PA DIV2
DIVIDER
SDM
PRE-EMPHASIS
FILTER
DSSS MOD
PABIAOP_ATB4
PAVSUP_ATB3
EXT PA
INTERFACE
CHARGE-
PUMP
LOOP FILTER
PFD
WAKE-UP CTRL
PA BATTERY TEMPERATURE ANALOG
RAMP MONITOR
SENSOR
TEST
LDO1
LDO2
LDO3
LDO4 BIAS
26MHz
OSC
RC
CAL
TIMER UNIT
32kHz
RC
OSC
32kHz
XTAL
OSC
4kB
PROGRAM
ROM
2kB
PROGRAM
RAM
256- BYTE
PACKET
RAM
64-BYTE
BBRAM
256-BYTE
MCR
SPI
EXT LNA/PA
ENABLE
GPIO
SPORT
IRQ
CS
MOSI
SCLK
MISO
RXEN_GP6
TXEN_GP5
TRCLK_CKO_GP3
DT_GP1
DR_GP0
IRQ1_GP4
IRQ2_TRFS_GP2
CREGRF1, CREGVCO CREGSYNTH CREGDIG1, RBIAS XOSC26P XOSC26N
CREGRF2,
CREGDIG2
CREGRF3
XOSC32KN_ATB2 XOSC32KP_GP7_ATB1
Figure 2. Detailed Functional Block Diagram
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Rev. 0 | Page 4 of 72



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