ADF4217L Datasheet PDF - Analog Devices

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ADF4217L
Analog Devices

Part Number ADF4217L
Description Dual Low Power Frequency Synthesizers
Page 24 Pages


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a
Dual Low Power
Frequency Synthesizers
ADF4217L/ADF4218L/ADF4219L
FEATURES
Total IDD: 7.1 mA
Bandwidth/RF 3.0 GHz
ADF4217L/ADF4218L, IF 1.1 GHz
ADF4219L, IF 1.0 GHz
2.6 V to 3.3 V Power Supply
1.8 V Logic Compatibility
Separate VP Allows Extended Tuning Voltage
Selectable Dual Modulus Prescaler
Selectable Charge Pump Currents
Charge Pump Current Matching of 1%
3-Wire Serial Interface
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS, WCDMA)
Wireless LANs
Communications Test Equipment
Cable TV Tuners (CATV)
GENERAL DESCRIPTION
The ADF4217L/ADF4218L/ADF4219L are low power dual
frequency synthesizers that can be used to implement local
oscillators in the up-conversion and down-conversion sections
of wireless receivers and transmitters. They can provide the LO
for both the RF and IF sections. They consist of a low noise
digital PFD (phase frequency detector), a precision charge pump, a
programmable reference divider, programmable A and B counters,
and a dual modulus prescaler (P/P + 1). The A and B counters,
in conjunction with the dual modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R Counter) allows selectable REFIN fre-
quencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizers are used with an
external loop filter and VCOs (voltage controlled oscillators).
Control of all the on-chip registers is via a simple 3-wire interface
with 1.8 V compatibility. The devices operate with a power supply
ranging from 2.6 V to 3.3 V and can be powered down when
not in use.
IFINA
IFINB
ADF4217L
ADF4218L
ONLY
REFIN
CLOCK
DATA
LE
RFINA
RFINB
FUNCTIONAL BLOCK DIAGRAM
ADF4219L ONLY
NC VDD1 VDD2
VP1
VP2
N = BP + A
IF
PRESCALER
BUFFER
11(13)-BIT IF
B COUNTER
6(5)-BIT IF
A COUNTER
PHASE
COMPARATOR
ADF4217L/
ADF4218L/
ADF4219L
CHARGE
PUMP
CPIF
IF
LOCK
DETECT
22-BIT
DATA SDOUT
REGISTER
14(15)-BIT IF
R COUNTER
14(15)-BIT RF
R COUNTER
OUTPUT
MUX
MUXOUT
RF
LOCK
DETECT
N = BP + A
RF
PRESCALER
11(13)-BIT RF
B COUNTER
6(5)-BIT RF
A COUNTER
PHASE
COMPARATOR
CHARGE
PUMP
CPRF
REV. C
FEATURES IN ( ) REFER TO ADF4219L
NC = NO CONNECT
DGNDRF AGNDRF DGNDIF AGNDIF
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.



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ADF4217L/ADF4218L/ADF4219L–SPECIFICATIONS1
(VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN)
ADF4217L, ADF4218L
ADF4217L, ADF4218L
ADF4219L
RF Input Sensitivity
ADF4217L, ADF4218L
ADF4219L
IF Input Frequency (IFIN)
ADF4217L/ADF4218L
ADF4219L P = 16/17
ADF4219L P = 8/9
IF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency3
REFIN CHARACTERISTICS
Reference Input Frequency
Reference Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency4
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
Reference Input Current
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
VDD1
VDD2
VP1, VP2
IDD (RF + IF)5
(RF only)5
(IF only)5
IP (IP1 + IP2)
Low Power Sleep Mode
BChips2
B Version1 (Typical)
0.15/3.0
0.15/2.5
0.8/2.2
–15/0
–20/0
0.045/1.1
0.045/1.0
0.045/0.55
–15/0
188
10/110
0.5
10
± 100
0.15/3.0
0.15/2.5
0.8/2.2
–15/0
–20/0
0.045/1.1
0.045/1.0
0.045/0.55
–15/0
188
10/110
0.5
10
± 100
Unit
Test Conditions/Comments
Use a square wave for operation
below minimum frequency spec.
GHz min/max
GHz min/max
GHz min/max
–10 dBm minimum input signal
–15 dBm minimum input signal
–20 dBm minimum input signal
dBm min/max
dBm min/max
GHz min/max
GHz min/max
GHz min/max
dBm min/max
–15 dBm minimum input signal
–10 dBm minimum input signal
–10 dBm minimum input signal
MHz max
MHz min/max
V p-p min
pF max
µA max
For f < 10 MHz, use dc-coupled
square wave, (0 to VDD).
AC-coupled. When dc-coupled,
0 to VDD max.
(CMOS compatible)
56 56 MHz max
4 4 mA typ
1 1 mA typ
1 1 % typ
1 1 nA typ
6
6
% max
0.5 V < VCP < VP – 0.5, 1% typ
5
5
% max
0.5 V < VCP < VP – 0.5, 0.1% typ
2
2
% typ
VCP = VP/2
1.4
0.6
±1
10
± 100
1.4
0.6
±1
10
± 100
V min
V max
µA max
pF max
µA max
VDD – 0.4
0.4
VDD – 0.4
0.4
V min
V max
IOH = 1 mA
IOL = 1 mA
2.6/3.3
VDD1
VDD1/5.5 V
10
7
5
0.6
1
2.6/3.3
VDD1
VDD1/5.5 V
10
7
5
0.6
1
V min/V max
V min/V max
mA max
mA
mA
mA typ
µA typ
7.1 mA typ
4.7 mA typ
3.4 mA typ
TA = 25°C
–2– REV. C



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ADF4217L/ADF4218L/ADF4219L
Parameter
NOISE CHARACTERISTICS6
RF Phase Noise Floor7
IF Phase Noise Floor7
Phase Noise Performance8
RF9
RF10
IF11
IF12
Spurious Signals
RF9
RF10
IF11
IF12
BChips2
B Version1 (Typical)
Unit
–171
–163
–167
–159
–75
–90
–77
–86
–78/–85
–80/–84
–79/–86
–80/–84
–171
–163
–167
–159
–75
–90
–77
–86
–78/–85
–80/–84
–79/–86
–80/–84
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc typ
dBc typ
dBc typ
dBc typ
Test Conditions/Comments
@ 30 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 30 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
1.95 GHz Output; 30 kHz PFD
900 MHz Output; 200 kHz PFD
900 MHz Output; 30 kHz PFD
900 MHz Output; 200 kHz PFD
Measured at Offset of fPFD/2fPFD
NOTES
1Operating temperature range is as follows: B Version: –40°C to +85°C.
2The BChip specifications are given as typical values.
3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
that is less than this value.
4Guaranteed by design. Sample tested to ensure compliance.
5This includes relevant IP.
6VDD = 3 V; P = 16/32; IFIN /RFIN for ADF4218L, ADF4219L = 540 MHz/900 MHz.
7The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
8The phase noise is measured with the EVAL-ADF421xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN
for the synthesizer. (fREFOUT = 10 MHz @ 0 dBm.)
9fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 1 kHz; fRF = 1.95 GHz; N = 65000; Loop B/W = 3 kHz
10fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz
11fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 1 kHz; fIF = 900 MHz; N = 30000; Loop B/W = 3 kHz
12fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fIF = 900 MHz; N = 4500; Loop B/W = 20 kHz
Specifications subject to change without notice.
TIMING CHARACTERISTICS (VDD1 = VDD2 = 3 V ؎ 10%, 5 V ؎ 10%; VDD1, VDD2 VP1,
VP2 6.0 V ; AGNDRF1 = DGNDRF1 = AGNDRF2 = DGNDRF2 = 0 V; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
Limit at
TMIN to TMAX
(B Version)
t1 10
t2 10
t3 25
t4 25
t5 10
t6 50
Guaranteed by design but not production tested.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
REV. C
CLOCK
DATA DB21 (MSB)
LE
LE
t1 t2
DB20
t3 t4
DB2
DB1
(CONTROL BIT C2)
Figure 1. Timing Diagram
–3–
DB0 (LSB)
(CONTROL BIT C1)
t6
t5



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ADF4217L/ADF4218L/ADF4219L
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C, unless otherwise noted.)
VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V
VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V
VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
REFIN, RF1IN (A, B), IFIN (A, B)
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
RFINA to RFINB . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 320 mV
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP JA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
LGA JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W
Lead Temperature, Soldering
TSSOP, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . 215°C
TSSOP, Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . 220°C
LGA, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . 240°C
LGA, Infrared (20 sec) . . . . . . . . . . . . . . . . . . . . . . . 240°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operationalsections
of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2This device is a high performance RF integrated circuit with an ESD rating of
< 2 kV and is ESD sensitive. Proper precautions should be taken for handling and
assembly.
3GND = AGND = DGND = 0 V.
Model
ADF4217L/ADF4218L/ADF4219LBRU
ADF4217L/ADF4218L/ADF4219LBCC
*Contact the factory for chip availability.
ORDERING GUIDE
Temperature
Range
–40°C to +85°C
–40°C to +85°C
Package
Description
Thin Shrink Small Outline Package (TSSOP)
Chip Array CASON (LGA)
Package
Option*
RU-20
CC-24
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the ADF4217L/
ADF4218L/ADF4219L feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4– REV. C



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