ADF4117 Datasheet PDF - Analog Devices

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ADF4117
Analog Devices

Part Number ADF4117
Description RF PLL Frequency Synthesizers
Page 28 Pages


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RF PLL Frequency Synthesizers
ADF4116/ADF4117/ADF4118
FEATURES
GENERAL DESCRIPTION
ADF4116: 550 MHz
ADF4117: 1.2 GHz
ADF4118: 3.0 GHz
2.7 V to 5.5 V power supply
Separate VP allows extended tuning voltage in 3 V systems
Y Grade: −40°C to +125°C
Dual-modulus prescaler
ADF4116: 8/9
ADF4117/ADF4118: 32/33
3-wire serial interface
Digital lock detect
Power-down mode
Fastlock mode
The ADF411x family of frequency synthesizers can be used to
implement local oscillators (LO) in the upconversion and
downconversion sections of wireless receivers and transmitters.
They consist of a low noise digital phase frequency detector
(PFD), a precision charge pump, a programmable reference
divider, programmable A and B counters, and a dual-modulus
prescaler (P/P + 1). The A (5-bit) and B (13-bit) counters, in
conjunction with the dual-modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R counter) allows selectable REFIN frequencies
at the PFD input. A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO).
APPLICATIONS
All of the on-chip registers are controlled via a simple 3-wire
Base stations for wireless radio
(GSM, PCS, DCS, CDMA, WCDMA)
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
Wireless handsets
(GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications test equipment
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP CPGND
ADF4116/ADF4117/ADF4118
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
21-BIT
INPUT REGISTER 19
FUNCTION
LATCH
SDOUT
FROM
FUNCTION LATCH
A, B COUNTER
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
5-BIT
A COUNTER
18
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
AVDD
SDOUT
5
CE
AGND
DGND
Figure 1.
CHARGE
PUMP
MUX
HIGH Z
M3 M2 M1
FLO
SWITCH
CP
MUXOUT
FLO
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
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ADF4116/ADF4117/ADF4118
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 12
Reference Input Section............................................................. 12
RF Input Stage............................................................................. 12
Prescaler (P/P + 1)...................................................................... 12
A Counter and B Counter ......................................................... 12
R Counter .................................................................................... 12
Phase Frequency Detector (PFD) and Charge Pump............ 13
MUXOUT and Lock Detect...................................................... 13
Input Shift Register..................................................................... 13
REVISION HISTORY
4/07—Rev. C to Rev. D
Changes to REFIN Characteristics Section..................................... 3
Changes to Table 4............................................................................ 7
Changes to Figure 35...................................................................... 22
Changes to Ordering Guide .......................................................... 25
11/05—Rev. B to Rev. C
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Table 3............................................................................ 6
Changes to Table 4............................................................................ 7
Changed OSC 3B1-13M0 to FOX801BH-130 ............................ 21
Changes to Ordering Guide .......................................................... 25
Latch Summaries ........................................................................ 14
Latch Maps .................................................................................. 15
Function Latch................................................................................ 19
Counter Reset ............................................................................. 19
Power-Down ............................................................................... 19
MUXOUT Control..................................................................... 19
Phase Detector Polarity ............................................................. 19
Charge Pump Three-State......................................................... 19
Fastlock Enable Bit ..................................................................... 19
Fastlock Mode Bit....................................................................... 19
Timer Counter Control ............................................................. 19
Initialization Latch ..................................................................... 20
Device Programming After Initial Power-Up ........................ 20
Applications Information .............................................................. 21
Local Oscillator for the GSM Base Station Transmitter........ 21
Shutdown Circuit ....................................................................... 21
Direct Conversion Modulator .................................................. 21
Interfacing ................................................................................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
9/04—Rev. A to Rev. B
Changes to Specifications.................................................................3
Changes to Ordering Guide .......................................................... 25
3/01—Rev. 0 to Rev. A
4/00—Rev. 0: Initial Version
Rev. D | Page 2 of 28



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ADF4116/ADF4117/ADF4118
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; TA = TMIN to TMAX, unless otherwise
noted; dBm referred to 50 Ω.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Sensitivity
RF Input Frequency
ADF4116
ADF4117
ADF4118
Maximum Allowable Prescaler
Output Frequency3
REFIN CHARACTERISTICS
Reference Input Frequency
Reference Input Sensitivity4,5
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR FREQUENCY5
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
Reference Input Current
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
B Version1
−15 to 0
−10 to 0
80 to 550
45 to 550
0.1 to 1.2
0.1 to 3.0
0.2 to 3.0
165
200
5 to 100
0.4 to AVDD
0.7 to AVDD
10
±100
55
1
250
2.5
3
1
3
2
2
0.8 × DVDD
0.2 × DVDD
±1
10
±100
DVDD − 0.4
0.4
Y Version2 Unit
Test Conditions/Comments
−10 to 0
−10 to 0
0.1 to 3.0
165
200
dBm min to max
dBm min to max
MHz min to max
MHz min to max
GHz min to max
GHz min to max
GHz min to max
MHz max
MHz max
AVDD = 3 V
AVDD = 5 V
See Figure 26 for input circuit
Input level = −8 dBm; for lower frequencies,
ensure slew rate (SR) > 36 V/μs
Input level = −10 dBm
Input level = −15 dBm
AVDD, DVDD = 3 V
AVDD, DVDD = 5 V
5 to 100
0.4 to AVDD
0.7 to AVDD
10
±100
55
MHz min to max
V p-p min to max
V p-p min to max
pF max
μA max
MHz max
For f < 5 MHz, ensure SR > 100 V/μs
AVDD = 3.3 V, biased at AVDD/2
For f ≥ 10 MHz, AVDD = 5 V, biased at AVDD/2
1 mA typ
250 μA typ
2.5 % typ
25 nA max
16 nA typ
3 % typ
2 % typ
2 % typ
0.8 × DVDD
0.2 × DVDD
±1
10
± 100
V min
V max
μA max
pF max
μA max
DVDD − 0.4 V min
0.4 V max
0.5 V ≤ VCP ≤ VP − 0.5
0.5 V ≤ VCP ≤ VP − 0.5
VCP = VP/2
IOH = 500 μA
IOL = 500 μA
Rev. D | Page 3 of 28



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ADF4116/ADF4117/ADF4118
Parameter
POWER SUPPLIES
AVDD
DVDD
VP
IDD (AIDD + DIDD)6
ADF4116
ADF4117
ADF4118
IP
Low-Power Sleep Mode
NOISE CHARACTERISTICS
ADF4118 Normalized Phase Noise
Floor 7
Phase Noise Performance8
ADF4116 540 MHz Output9
ADF4117 900 MHz Output10
ADF4118 900 MHz Output10
ADF4117 836 MHz Output11
ADF4118 1750 MHz Output12
ADF4118 1750 MHz Output13
ADF4118 1960 MHz Output14
Spurious Signals
ADF4116 540 MHz Output10
ADF4117 900 MHz Output10
ADF4118 900 MHz Output 10
ADF4117 836 MHz Output11
ADF4118 1750 MHz Output12
ADF4118 1750 MHz Output13
ADF4118 1960 MHz Output14
B Version1 Y Version2 Unit
2.7 to 5.5
AVDD
AVDD to 6.0
2.7 to 5.5
AVDD
AVDD to 6.0
V min to V max
V min to V max
5.5 mA max
5.5 mA max
7.5 7.5 mA max
0.4 0.4 mA max
1 1 μA typ
−213
−213
dBc/Hz typ
−89 −89 dBc/Hz typ
−87 −87 dBc/Hz typ
−90 −90 dBc/Hz typ
−78 −78 dBc/Hz typ
−85 −85 dBc/Hz typ
−65 −65 dBc/Hz typ
−84 −84 dBc/Hz typ
−88/−99
−90/−104
−91/−100
−80/−84
−88/−90
−65/−73
−80/−86
−88/−99
−90/−104
−91/−100
−80/−84
−88/−90
−65/−73
−80/−86
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
Test Conditions/Comments
AVDD ≤ VP ≤ 6.0 V
4.5 mA typical
4.5 mA typical
6.5 mA typical
TA = 25°C
@ VCO output
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 300 Hz offset and 30 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 200 Hz offset and 10 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 30 kHz/60 kHz and 30 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 10 kHz/20 kHz and 10 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
1 Operating temperature range for the B version is −40°C to +85°C.
2 Operating temperature range for the Y version is −40°C to +125°C.
3 This is the maximum operating frequency of the CMOS counters.
4 AC coupling ensures AVDD/2 bias. See Figure 35 for typical circuit.
5 Guaranteed by design.
6 TA = 25°C; AVDD = DVDD = 3 V; RFIN for ADF4116 = 540 MHz; RFIN for ADF4117, ADF4118 = 900 MHz.
7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N
divider value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN.
8 The phase noise is measured with the EVAL-ADF411xEB and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer
(fREFOUT = 10 MHz @ 0 dBm).
9 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop bandwidth = 20 kHz.
10 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop bandwidth = 20 kHz.
11 fREFIN = 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop bandwidth = 3 kHz.
12 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop bandwidth = 20 kHz.
13 fREFIN = 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop bandwidth = 1 kHz.
14 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop bandwidth = 20 kHz.
Rev. D | Page 4 of 28



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