ADF4112 Datasheet PDF - Analog Devices

www.Datasheet-PDF.com

ADF4112
Analog Devices

Part Number ADF4112
Description RF PLL Frequency Synthesizers
Page 28 Pages


ADF4112 datasheet pdf
Download PDF
ADF4112 pdf
View PDF for Mobile

No Preview Available !

Data Sheet
RF PLL Frequency Synthesizers
ADF4110/ADF4111/ADF4112/ADF4113
FEATURES
GENERAL DESCRIPTION
ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz;
ADF4113: 4.0 GHz
2.7 V to 5.5 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler 8/9, 16/17, 32/33,
64/65
The ADF4110 family of frequency synthesizers can be used to
implement local oscillators in the upconversion and downcon-
version sections of wireless receivers and transmitters. They
consist of a low noise digital PFD (phase frequency detector), a
precision charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
Programmable charge pump currents
(P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction
Programmable antibacklash pulse width
with the dual-modulus prescaler (P/P + 1), implement an N
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
divider (N = BP + A). In addition, the 14-bit reference counter
(R counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
APPLICATIONS
Base stations for wireless radio (GSM, PCS, DCS, CDMA,
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO).
WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications test equipment
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
24-BIT
INPUT REGISTER 22
SDOUT
14-BIT
R COUNTER
14
R COUNTER
LATCH
FUNCTION
LATCH
A, B COUNTER
LATCH
19
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
LOCK
DETECT
CURRENT CURRENT
SETTING 1 SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
FROM
FUNCTION
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P +1
LOAD
LOAD
6-BIT
A COUNTER
AVDD
SDOUT
MUX
HIGH Z
M3 M2 M1
ADF4110/ADF4111
6 ADF4112/ADF4113
CE
AGND
DGND
Figure 1. Functional Block Diagram
CP
MUXOUT
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com



No Preview Available !

ADF4110/ADF4111/ADF4112/ADF4113
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 12
Reference Input Section............................................................. 12
RF Input Stage............................................................................. 12
Prescaler (P/P + 1)...................................................................... 12
A and B Counters ....................................................................... 12
R Counter .................................................................................... 12
Data Sheet
Phase Frequency Detector (PFD) and Charge Pump............ 13
Muxout and Lock Detect........................................................... 13
Input Shift Register .................................................................... 13
Function Latch............................................................................ 19
Initialization Latch ..................................................................... 20
Device Programming after Initial Power-Up ......................... 20
Resynchronizing the Prescaler Output.................................... 21
Applications..................................................................................... 22
Local Oscillator for GSM Base Station Transmitter .............. 22
Using a D/A Converter to Drive the RSET Pin......................... 23
Shutdown Circuit ....................................................................... 23
Wideband PLL ............................................................................ 23
Direct Conversion Modulator .................................................. 25
Interfacing ................................................................................... 26
PCB Design Guidelines for Chip Scale Package .................... 26
Outline Dimensions ....................................................................... 27
Ordering Guide............................................................................... 28
REVISION HISTORY
1/13—Rev. E to Rev. F
Changes to Table 1.............................................................................4
Changes to Ordering Guide ...........................................................28
8/12—Rev. D to Rev. E
Changed CP-20-1 to CP-20-6 ........................................... Universal
Updated Outline Dimensions ........................................................28
Changes to Ordering Guide ...........................................................28
5/12—Rev. C to Rev. D
Changes to Figure 2...........................................................................5
Changes to Figure 4 and Table 4......................................................7
Updated Outline Dimensions ........................................................28
Changes to Ordering Guide ...........................................................28
3/04—Data sheet changed from Rev. B to Rev. C.
Updated Format.................................................................. Universal
Changes to Specifications .................................................................2
Changes to Figure 32.......................................................................22
Changes to the Ordering Guide.....................................................28
3/03—Data sheet changed from Rev. A to Rev. B.
Edits to Specifications .......................................................................2
Updated OUTLINE DIMENSIONS .............................................24
1/01—Data sheet changed from Rev. 0 to Rev. A.
Changes to DC Specifications in B Version, B Chips,
Unit, and Test Conditions/Comments Columns .....................2
Changes to Absolute Maximum Rating .........................................4
Changes to FRINA Function Test .....................................................5
Changes to Figure 8...........................................................................7
New Graph Added—TPC 22 ...........................................................9
Change to PD Polarity Box in Table V .........................................15
Change to PD Polarity Box in Table VI........................................16
Change to PD Polarity Paragraph .................................................17
Addition of New Material
(PCB Design Guidelines for Chip–Scale package) ................23
Replacement of CP-20 Outline with CP-20 [2] Outline ............24
Rev. F | Page 2 of 28



No Preview Available !

Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; dBm referred to 50 Ω;
TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is as follows: B Version: −40°C to +85°C.
Table 1.
Parameter
RF CHARACTERISTICS (3 V)
RF Input Sensitivity
RF Input Frequency
ADF4110
ADF4110
ADF4111
ADF4112
ADF4112
ADF4113
Maximum Allowable Prescaler Output
Frequency2
RF CHARACTERISTICS (5 V)
RF Input Sensitivity
RF Input Frequency
ADF4110
ADF4111
ADF4112
ADF4113
ADF4113
Maximum Allowable Prescaler Output
Frequency2
REFIN CHARACTERISTICS
REFIN Input Frequency
Reference Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR FREQUENCY4
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP 3-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
B Version B Chips1
−15/0
−15/0
Unit
dBm min/max
Test Conditions/Comments
See Figure 29 for input circuit.
80/550
50/550
0.08/1.2
0.2/3.0
0.1/3.0
0.2/3.7
165
80/550
50/550
0.08/1.2
0.2/3.0
0.1/3.0
0.2/3.7
165
MHz min/max
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
For lower frequencies, ensure slew rate
(SR) > 30 V/µs.
Input level = −10 dBm.
For lower frequencies, ensure SR > 30 V/µs.
For lower frequencies, ensure SR > 75 V/µs.
Input level = −10 dBm.
Input level = −10 dBm. For lower frequencies,
ensure SR > 130 V/µs.
MHz max
−10/0
−10/0
dBm min/max
80/550
0.08/1.4
0.1/3.0
0.2/3.7
0.2/4.0
200
80/550
0.08/1.4
0.1/3.0
0.2/3.7
0.2/4.0
200
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
For lower frequencies, ensure SR > 50 V/µs.
For lower frequencies, ensure SR > 50 V/µs.
For lower frequencies, ensure SR > 75 V/µs.
For lower frequencies, ensure SR > 130 V/µs.
Input level = −5 dBm.
MHz max
5/104
0.4/AVDD
3.0/AVDD
10
±100
55
5/104
0.4/AVDD
3.0/AVDD
10
±100
55
MHz min/max
V p-p min/max
V p-p min/max
pF max
µA max
MHz max
For f < 5 MHz, ensure SR > 100 V/µs.
AVDD = 3.3 V, biased at AVDD/2. See Note 3.
AVDD = 5 V, biased at AVDD/2. See Note 3.
5
625
2.5
2.7/10
1
2
1.5
2
5
625
2.5
2.7/10
1
2
1.5
2
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
Programmable (see Table 9).
With RSET = 4.7 kΩ.
With RSET = 4.7 kΩ.
See Table 9.
0.5 V ≤ VCP ≤ VP – 0.5 V.
0.5 V ≤ VCP ≤ VP – 0.5 V.
VCP = VP/2.
0.8 × DVDD
0.2 × DVDD
±1
10
0.8 × DVDD
0.2 × DVDD
±1
10
V min
V max
µA max
pF max
DVDD – 0.4
0.4
DVDD – 0.4
0.4
V min
V max
IOH = 500 µA.
IOL = 500 µA.
Rev. F | Page 3 of 28



No Preview Available !

ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
Parameter
POWER SUPPLIES
AVDD
DVDD
VP
IDD5 (AIDD + DIDD)
ADF4110
ADF4111
ADF4112
ADF4113
IP
Low Power Sleep Mode
NOISE CHARACTERISTICS
ADF4113 Normalized Phase Noise Floor6
Phase Noise Performance7
ADF4110: 540 MHz Output8
ADF4111: 900 MHz Output9
ADF4112: 900 MHz Output9
ADF4113: 900 MHz Output9
ADF4111: 836 MHz Output10
ADF4112: 1750 MHz Output11
ADF4112: 1750 MHz Output12
ADF4112: 1960 MHz Output13
ADF4113: 1960 MHz Output13
ADF4113: 3100 MHz Output14
Spurious Signals
ADF4110: 540 MHz Output9
ADF4111: 900 MHz Output9
ADF4112: 900 MHz Output9
ADF4113: 900 MHz Output9
ADF4111: 836 MHz Output10
ADF4112: 1750 MHz Output11
ADF4112: 1750 MHz Output12
ADF4112: 1960 MHz Output13
ADF4113: 1960 MHz Output13
ADF4113: 3100 MHz Output14
B Version B Chips1 Unit
2.7/5.5
AVDD
AVDD/6.0
2.7/5.5
AVDD
AVDD/6.0
V min/V max
V min/V max
5.5 4.5 mA max
5.5 4.5 mA max
7.5 6.5 mA max
11 8.5 mA max
0.5 0.5 mA max
1 1 µA typ
−215
−215
dBc/Hz typ
−91 −91 dBc/Hz typ
−87 −87 dBc/Hz typ
−90 −90 dBc/Hz typ
−91 −91 dBc/Hz typ
−78 −78 dBc/Hz typ
−86 −86 dBc/Hz typ
−66 −66 dBc/Hz typ
−84 −84 dBc/Hz typ
−85 −85 dBc/Hz typ
−86 −86 dBc/Hz typ
−97/−106
−98/−110
−91/−100
−100/−110
−81/−84
−88/−90
−65/−73
−80/−84
−80/−84
−80/−82
−97/−106
−98/−110
−91/−100
−100/−110
−81/−84
−88/−90
−65/−73
−80/−84
−80/−84
−82/−82
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
Test Conditions/Comments
AVDD ≤ VP ≤ 6.0 V. See Figure 25 and Figure 26.
4.5 mA typical.
4.5 mA typical.
6.5 mA typical.
8.5 mA typical.
TA = 25°C.
@ VCO output.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 300 Hz offset and 30 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 200 Hz offset and 10 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 1 MHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 30 kHz/60 kHz and 30 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 10 kHz/20 kHz and 10 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 1 MHz/2 MHz and 1 MHz PFD frequency.
1The B chip specifications are given as typical values.
2This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3AC coupling ensures AVDD/2 bias. See Figure 33 for a typical circuit.
4Guaranteed by design.
5 TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz.
6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN.
7 The phase noise is measured with the EV-ADF411XSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the
synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (Table 7).
8 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop B/W = 20 kHz.
9 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz.
10 fREFIN = 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop B/W = 3 kHz.
11 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop B/W = 20 kHz
12 fREFIN = 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop B/W = 1 kHz.
13 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop B/W = 20 kHz.
14 fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; loop B/W = 20 kHz.
Rev. F | Page 4 of 28



ADF4112 datasheet pdf
Download PDF
ADF4112 pdf
View PDF for Mobile


Related : Start with ADF411 Part Numbers by
ADF4110 RF PLL Frequency Synthesizers ADF4110
Analog Devices
ADF4110 pdf
ADF4111 RF PLL Frequency Synthesizers ADF4111
Analog Devices
ADF4111 pdf
ADF4112 RF PLL Frequency Synthesizers ADF4112
Analog Devices
ADF4112 pdf
ADF4113 RF PLL Frequency Synthesizers ADF4113
Analog Devices
ADF4113 pdf
ADF4113HV High Voltage Charge Pump / PLL Synthesizer ADF4113HV
Analog Devices
ADF4113HV pdf
ADF4116 RF PLL Frequency Synthesizers ADF4116
Analog Devices
ADF4116 pdf
ADF4117 RF PLL Frequency Synthesizers ADF4117
Analog Devices
ADF4117 pdf
ADF4118 RF PLL Frequency Synthesizers ADF4118
Analog Devices
ADF4118 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact