ADF4107 Datasheet PDF - Analog Devices

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ADF4107
Analog Devices

Part Number ADF4107
Description PLL Frequency Synthesizer
Page 21 Pages


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Data Sheet
PLL Frequency Synthesizer
ADF4107
FEATURES
7.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio
GENERAL DESCRIPTION
The ADF4107 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion sections
of wireless receivers and transmitters. It consists of a low noise
digital PFD (phase frequency detector), a precision charge pump, a
programmable reference divider, programmable A and B counters,
and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B
(13-bit) counters, in conjunction with the dual-modulus
prescaler (P/P + 1), implement an N divider (N = BP + A). In
addition, the 14-bit reference counter (R counter), allows
selectable REFIN frequencies at the PFD input. A complete PLL
(phase-locked loop) can be implemented if the synthesizer is
used with an external loop filter and VCO (voltage controlled
oscillator). Its very high bandwidth means that frequency
doublers can be eliminated in many high frequency systems,
simplifying system architecture and reducing cost.
AVDD DVDD
FUNCTIONAL BLOCK DIAGRAM
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
24-BIT INPUT
REGISTER 22
FUNCTION
LATCH
SDOUT
FROM
FUNCTION
LATCH
A, B COUNTER
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
6-BIT
A COUNTER
CE AGND DGND
6
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
HIGH Z
19 AVDD
MUX
MUXOUT
SDOUT
M3 M2 M1
ADF4107
Figure 1.
Rev. D
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ADF4107* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• ADF4107 Evaluation Board
Documentation
Application Notes
• AN-30: Ask the Applications Engineer - PLL Synthesizers
• AN-349: Keys to Longer Life for CMOS
• AN-873: Lock Detect on the ADF4xxx Family of PLL
Synthesizers
Data Sheet
• ADF4107: PLL Frequency Synthesizer Data Sheet
User Guides
• UG-161: PLL Frequency Synthesizer Evaluation Board
• UG-476: PLL Software Installation Guide
Tools and Simulations
• ADIsimPLL™
• ADIsimRF
• dt_ADF411x_Register_Configuration
Reference Materials
Product Selection Guide
• RF Source Booklet
Technical Articles
• Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 1
• Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 3
• Phase-Locked Loops for High-Frequency Receivers and
Transmitters - Part 2
Design Resources
• ADF4107 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
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Sample and Buy
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Technical Support
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ADF4107
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Functional Description .................................................................... 9
Reference Input Stage................................................................... 9
RF Input Stage............................................................................... 9
Prescaler (P/P + 1)........................................................................ 9
A and B Counters ......................................................................... 9
R Counter ...................................................................................... 9
REVISION HISTORY
3/13—Rev. C to Rev. D
Changed RFINA to RFINB Parameter from ±320 mV to ±600 mV,
Table 3 ................................................................................................ 5
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
11/12—Rev. B to Rev. C
Changed EVAL-ADF411xEBZ1 to EV-ADF411XSD1Z ............. 4
Changes to Table 3............................................................................ 5
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
9/11—Rev. A to Rev. B
Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter,
Table 1 ................................................................................................ 3
Added Normalized 1/f Noise (PN1_f) Parameter and Endnote 11,
Table 1 ................................................................................................ 3
Changed EVAL-ADF4107EB1 to EVAL-ADF411xEBZ1............ 4
Changes to Figure 4 and Table 4..................................................... 6
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
Data Sheet
Phase Frequency Detector and Charge Pump ..............................9
MUXOUT and Lock Detect...................................................... 10
Input Shift Register .................................................................... 10
Latch Summary........................................................................... 11
Reference Counter Latch Map.................................................. 12
AB Counter Latch Map ............................................................. 13
Function Latch Map................................................................... 14
Initialization Latch Map ............................................................ 15
Function Latch............................................................................ 16
Initialization Latch ..................................................................... 17
Device Programming after Initial Power-Up ............................. 17
Applications..................................................................................... 18
Local Oscillator for LMDS Base Station Transmitter............ 18
Interfacing ................................................................................... 19
PCB Design Guidelines for Chip Scale Package .................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
4/07—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to REFIN Characteristics Section ...................................3
Changes to Noise Characteristics Section......................................4
Changes to Absolute Maximum Ratings Section..........................5
Changes to Figure 23...................................................................... 12
Changes to Ordering Guide .......................................................... 20
5/03—Revision 0: Initial Version
Rev. D | Page 2 of 20



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Data Sheet
ADF4107
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN,
unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN)3
RF Input Sensitivity
Maximum Allowable Prescaler Output
Frequency4
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity5
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency7
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
B Version1
1.0/7.0
–5/+5
300
20/250
0.8/VDD
10
±100
104
5
625
2.5
3.0 to 11
1
2
1.5
2
1.4
0.6
±1
10
1.4
VOH, Output High Voltage
IOH
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD8 (AIDD + DIDD)
IP
Power-Down Mode9 (AIDD + DIDD)
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PNSYNTH)10
VDD − 0.4
100
0.4
2.7/3.3
AVDD
AVDD/5.5
17
0.4
10
−223
Normalized 1/f Noise (PN1_f)11
−122
B Chips2 (Typ) Unit
Test Conditions/Comments
1.0/7.0
–5/+5
300
GHz min/max
dBm min/max
MHz max
See Figure 18 for input circuit
20/250
0.8/VDD
10
±100
104
5
625
2.5
3.0 to 11
1
2
1.5
2
1.4
0.6
±1
10
1.4
VDD − 0.4
100
0.4
2.7/3.3
AVDD
AVDD/5.5
15
0.4
10
−223
−122
MHz min/max
V p-p min/max
pF max
µA max
For f < 20 MHz, ensure slew rate >50 V/µs
Biased at AVDD/26
MHz max
ABP = 0,0 (2.9 ns antibacklash pulse width)
Programmable; see Figure 25
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
See Figure 25
0.5 V ≤ VCP ≤ VP − 0.5 V
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
V min
V max
µA max
pF max
V min
V min
µA max
V max
Open-drain output chosen; 1 kΩ pull-up
resistor to 1.8 V
CMOS output chosen
IOL = 500 µA
V min/V max
V min/V max
mA max
mA max
µA typ
AVDD ≤ VP ≤ 5.5 V
15 mA typ
TA = 25°C
dBc/Hz typ
dBc/Hz typ
PLL loop BW = 500 kHz, measured at
100 kHz offset
10 kHz offset; normalized to 1 GHz
Rev. D | Page 3 of 20



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