AD9958 Datasheet PDF - Analog Devices

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AD9958
Analog Devices

Part Number AD9958
Description 500 MSPS DDS
Page 30 Pages


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Data Sheet
FEATURES
2 synchronized DDS channels @ 500 MSPS
Independent frequency/phase/amplitude control between
channels
Matched latencies for frequency/phase/amplitude changes
Excellent channel-to-channel isolation (>72 dB)
Linear frequency/phase/amplitude sweeping capability
Up to 16 levels of frequency/phase/amplitude modulation
(pin-selectable)
2 integrated 10-bit digital-to-analog converters (DACs)
Individually programmable DAC full-scale currents
0.12 Hz or better frequency tuning resolution
14-bit phase offset resolution
10-bit output amplitude scaling resolution
Serial I/O port interface (SPI) with 800 Mbps data throughput
Software-/hardware-controlled power-down
Dual supply operation (1.8 V DDS core/3.3 V serial I/O)
Multiple device synchronization
Selectable 4× to 20× REFCLK multiplier (PLL)
Selectable REFCLK crystal oscillator
56-lead LFCSP
2-Channel, 500 MSPS DDS
with 10-Bit DACs
AD9958
APPLICATIONS
Agile local oscillators
Phased array radars/sonars
Instrumentation
Synchronized clocking
RF source for AOTF
Single-side band suppressed carriers
Quadrature communications
FUNCTIONAL BLOCK DIAGRAM
AD9958
(2)
500MSPS
DDS CORES
10-BIT
DAC
10-BIT
DAC
RECONSTRUCTED
SINE WAVE
RECONSTRUCTED
SINE WAVE
SYSTEM
CLOCK
SOURCE
MODULATION CONTROL
REF CLOCK
INPUT CIRCUITRY
TIMING AND
CONTROL
USER INTERFACE
Figure 1.
Rev. C
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AD9958
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Application Circuits ....................................................................... 14
Equivalent Input and Output Circuits ......................................... 17
Theory of Operation ...................................................................... 18
DDS Core..................................................................................... 18
Digital-to-Analog Converter .................................................... 18
Modes of Operation ....................................................................... 19
Channel Constraint Guidelines ................................................ 19
Power Supplies ............................................................................ 19
Single-Tone Mode ...................................................................... 19
Reference Clock Modes ............................................................. 20
Scalable DAC Reference Current Control Mode ................... 21
Power-Down Functions............................................................. 21
Modulation Mode....................................................................... 21
Modulation Using SDIO_x Pins for RU/RD .......................... 24
REVISION HISTORY
11/2016—Rev. B to Rev. C
Change to Figure 37 Caption ........................................................ 26
4/2013—Rev. A to Rev. B
Changes to Linear Sweep Mode Section and Setting the Slope of
the Linear Sweep............................................................................. 25
Changes to Figure 38 and Figure 39 Captions............................ 27
Changes to Ramp Rate Timer Section......................................... 28
Updated Outline Dimensions ....................................................... 44
7/2008—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Inserted Figure 1; Renumbered Sequentially................................ 1
Changes to Input Level Parameter in Table 1 ............................... 4
Added Profile Pin Toggle Rate Parameter in Table 1................... 6
Changes to Layout ............................................................................ 8
Changes to Table 3............................................................................ 9
Added Equivalent Input and Output Circuits Section .............. 17
Changes to Reference Clock Input Circuitry Section................ 20
Data Sheet
Linear Sweep Mode.................................................................... 25
Linear Sweep No-Dwell Mode ................................................. 26
Sweep and Phase Accumulator Clearing Functions .............. 27
Output Amplitude Control Mode............................................ 28
Synchronizing Multiple AD9958 Devices................................... 29
Automatic Mode Synchronization ........................................... 29
Manual Software Mode Synchronization................................ 29
Manual Hardware Mode Synchronization.............................. 29
I/O_UPDATE, SYNC_CLK, and System Clock
Relationships............................................................................... 30
Serial I/O Port ................................................................................. 31
Overview ..................................................................................... 31
Instruction Byte Description .................................................... 32
Serial I/O Port Pin Description ................................................ 32
Serial I/O Port Function Description ...................................... 32
MSB/LSB Transfer Description ................................................ 32
Serial I/O Modes of Operation................................................. 33
Register Maps and Bit Descriptions............................................. 36
Register Maps.............................................................................. 36
Descriptions for Control Registers .......................................... 39
Descriptions for Channel Registers ......................................... 41
Outline Dimensions ....................................................................... 44
Ordering Guide .......................................................................... 44
Change to Figure 35 ....................................................................... 21
Changes to Setting the Slope of the Linear Sweep Section ....... 25
Changes to Figure 37...................................................................... 26
Changes to Figure 38 and Figure 39 ............................................ 27
Changes to Figure 40...................................................................... 30
Added Table 25; Renumbered Sequentially ................................ 31
Changes to Figure 41...................................................................... 31
Changes to Figure 42, Serial Data I/O (SDIO_0, SDIO_1,
SDIO_3) Section, and Added Example Instruction Byte
Section.............................................................................................. 32
Added Table 27 ............................................................................... 33
Changes to Figure 46, Figure 47, Figure 48, and Figure 49 ...... 35
Changes to Register Maps and Bit Descriptions Section and
Added Endnote 2 to Table 28........................................................ 36
Added Endnote 1 to Table 30........................................................ 38
Added Exposed Pad Notation to Outline Dimensions ............. 44
9/2005—Revision 0: Initial Version
Rev. C | Page 2 of 44



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Data Sheet
GENERAL DESCRIPTION
The AD9958 consists of two DDS cores that provide indepen-
dent frequency, phase, and amplitude control on each channel.
This flexibility can be used to correct imbalances between
signals due to analog processing, such as filtering, amplification,
or PCB layout related mismatches. Because both channels share
a common system clock, they are inherently synchronized.
Synchronization of multiple devices is supported.
The AD9958 can perform up to a 16-level modulation of
frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is
performed by applying data to the profile pins. In addition, the
AD9958 also supports linear sweep of frequency, phase, or
amplitude for applications such as radar and instrumentation.
The AD9958 serial I/O port offers multiple configurations to
provide significant flexibility. The serial I/O port offers an SPI-
compatible mode of operation that is virtually identical to the
SPI operation found in earlier Analog Devices, Inc., DDS
products. Flexibility is provided by four data pins (SDIO_0/
SDIO_1/SDIO_2/SDIO_3) that allow four programmable
modes of serial I/O operation.
The AD9958 uses advanced DDS technology that provides low
power dissipation with high performance. The device incorporates
two integrated, high speed 10-bit DACs with excellent wideband
and narrow-band SFDR. Each channel has a dedicated 32-bit
frequency tuning word, 14 bits of phase offset, and a 10-bit
output scale multiplier.
AD9958
The DAC outputs are supply referenced and must be termin-
ated into AVDD by a resistor or an AVDD center-tapped
transformer. Each DAC has its own programmable reference to
enable different full-scale currents for each channel.
The DDS acts as a high resolution frequency divider with the
REFCLK as the input and the DAC providing the output. The
REFCLK input source is common to both channels and can be
driven directly or used in combination with an integrated
REFCLK multiplier (PLL) up to a maximum of 500 MSPS. The
PLL multiplication factor is programmable from 4 to 20, in
integer steps. The REFCLK input also features an oscillator
circuit to support an external crystal as the REFCLK source.
The crystal must be between 20 MHz and 30 MHz. The crystal
can be used in combination with the REFCLK multiplier.
The AD9958 comes in a space-saving 56-lead LFCSP package.
The DDS core (AVDD and DVDD pins) is powered by a 1.8 V
supply. The digital I/O interface (SPI) operates at 3.3 V and
requires the pin labeled DVDD_I/O (Pin 49) be connected
to 3.3 V.
The AD9958 operates over the industrial temperature range of
−40°C to +85°C.
AD9958
32 Σ
32
32 Σ
32
SYNC_IN
SYNC_OUT
I/O_UPDATE
SYNC_CLK
REF_CLK
REF_CLK
FTW
FTW 32
÷4
BUFFER/
XTAL
OSCILLATOR
REF CLOCK
MULTIPLIER
4× TO 20×
CLK_MODE_SEL
DDS CORE
Σ
Σ
15 COS(X)
10
10 DAC
DDS CORE
Σ
Σ
15 COS(X)
10
10 DAC
PHASE/
PHASE
14
AMP/ 10
AMP
SCALABLE
DAC REF
CURRENT
TIMING AND CONTROL LOGIC
SYSTEM
CLK
CONTROL
REGISTERS
MUX
CHANNEL
REGISTERS
1.8V
1.8V
PROFILE
REGISTERS
AVDD DVDD
P0 P1 P2 P3
Figure 2. Detailed Block Diagram
I/O
PORT
BUFFER
DVDD_I/O
CH0_IOUT
CH0_IOUT
CH1_IOUT
CH1_IOUT
DAC_RSET
PWR_DWN_CTL
MASTER_RESET
SCLK
CS
SDIO_0
SDIO_1
SDIO_2
SDIO_3
Rev. C | Page 3 of 44



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AD9958
Data Sheet
SPECIFICATIONS
AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; T = 25°C; RSET = 1.91 kΩ; external reference clock frequency = 500 MSPS
(REFCLK multiplier bypassed), unless otherwise noted.
Table 1.
Parameter
REFERENCE CLOCK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Bypassed
REFCLK Multiplier Enabled
Internal VCO Output Frequency Range
VCO Gain Control Bit Set High1
VCO Gain Control Bit Set Low1
Crystal REFCLK Source Range
Input Level
Input Voltage Bias Level
Input Capacitance
Input Impedance
Duty Cycle with REFCLK Multiplier Bypassed
Duty Cycle with REFCLK Multiplier Enabled
CLK Mode Select (Pin 24) Logic 1 Voltage
CLK Mode Select (Pin 24) Logic 0 Voltage
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Channel-to-Channel Output Amplitude Matching Error
Output Current Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Voltage Compliance Range
Channel-to-Channel Isolation
WIDEBAND SFDR
1 MHz to 20 MHz Analog Output
20 MHz to 60 MHz Analog Output
60 MHz to 100 MHz Analog Output
100 MHz to 150 MHz Analog Output
150 MHz to 200 MHz Analog Output
NARROW-BAND SFDR
1.1 MHz Analog Output (±10 kHz)
1.1 MHz Analog Output (±50 kHz)
1.1 MHz Analog Output (±250 kHz)
1.1 MHz Analog Output (±1 MHz)
15.1 MHz Analog Output (±10 kHz)
15.1 MHz Analog Output (±50 kHz)
15.1 MHz Analog Output (±250 kHz)
15.1 MHz Analog Output (±1 MHz)
40.1 MHz Analog Output (±10 kHz)
40.1 MHz Analog Output (±50 kHz)
40.1 MHz Analog Output (±250 kHz)
40.1 MHz Analog Output (±1 MHz)
75.1 MHz Analog Output (±10 kHz)
Min Typ
1
10
255
100
20
200
1.15
2
1500
45
35
1.25
1.25
−10
−2.5
AVDD −
0.50
72
1
±0.5
±1.0
3
−65
−62
−59
−56
−53
−90
−88
−86
−85
−90
−87
−85
−83
−90
−87
−84
−82
−87
Max Unit
500 MHz
125 MHz
500
160
30
1000
55
65
1.8
0.5
MHz
MHz
MHz
mV
V
pF
%
%
V
V
10
10
+10
+2.5
25
AVDD +
0.50
Bits
mA
% FS
%
µA
LSB
LSB
pF
V
dB
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Test Conditions/Comments
See Figure 34 and Figure 35
Measured at each pin (single-ended)
1.8 V digital input logic
1.8 V digital input logic
Must be referenced to AVDD
DAC supplies tied together (see Figure 19)
The frequency range for wideband SFDR
is defined as dc to Nyquist
Rev. C | Page 4 of 44



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