AD9957 Datasheet PDF - Analog Devices

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AD9957
Analog Devices

Part Number AD9957
Description 1 GSPS Quadrature Digital Upconverter
Page 30 Pages


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Data Sheet
1 GSPS Quadrature Digital Upconverter
with 18-Bit I/Q Data Path and 14-Bit DAC
AD9957
FEATURES
1 GSPS internal clock speed (up to 400 MHz analog output)
Integrated 1 GSPS 14-bit DAC
250 MSPS input data rate
Phase noise ≤ −125 dBc/Hz (400 MHz carrier @ 1 kHz offset)
Excellent dynamic performance >80 dB narrow-band SFDR
8 programmable profiles for shift keying
Sin(x)/(x) correction (inverse sinc filter)
Reference clock multiplier
Internal oscillator for a single crystal operation
Software and hardware controlled power-down
Integrated RAM
Phase modulation capability
Multichip synchronization
Easy interface to Blackfin SPORT
Interpolation factors from 4× to 252×
Interpolation DAC mode
Gain control DAC
Internal divider allows references up to 2 GHz
1.8 V and 3.3 V power supplies
100-lead TQFP_EP package
APPLICATIONS
HFC data, telephony, and video modems
Wireless base station transmissions
Broadband communications transmissions
Internet telephony
GENERAL DESCRIPTION
The AD9957 functions as a universal I/Q modulator and agile
upconverter for communications systems where cost, size, power
consumption, and dynamic performance are critical. The
AD9957 integrates a high speed, direct digital synthesizer
(DDS), a high performance, high speed, 14-bit digital-to-analog
converter (DAC), clock multiplier circuitry, digital filters, and
other DSP functions onto a single chip. It provides baseband
upconversion for data transmission in a wired or wireless
communications system.
The AD9957 is the third offering in a family of quadrature
digital upconverters (QDUCs) that includes the AD9857 and
AD9856. It offers performance gains in operating speed, power
consumption, and spectral performance. Unlike its predecessors,
it supports a 16-bit serial input mode for I/Q baseband data.
The device can alternatively be programmed to operate either as
a single tone, sinusoidal source or as an interpolating DAC.
The reference clock input circuitry includes a crystal oscillator,
a high speed, divide-by-two input, and a low noise PLL for
multiplication of the reference clock frequency.
The user interface to the control functions includes a serial port
easily configured to interface to the SPORT of the Blackfin®
DSP and profile pins to enable fast and easy shift keying of any
signal parameter (phase, frequency, or amplitude).
I/Q DATA
FUNCTIONAL BLOCK DIAGRAM
FORMAT AND
INTERPOLATE
I
Q
14-BIT DAC
NCO AD9957
DATA
FOR
XMIT
TIMING
AND
CONTROL
REFERENCE CLOCK
INPUT CIRCUITRY
USER INTERFACE
REFERENCE CLOCK INPUT
Figure 1.
Rev. D
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AD9957* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
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Evaluation Kits
• AD9957 Evaluation Board
Documentation
Application Notes
• AN-0996: The Advantages of Using a Quadrature Digital
Upconverter (QDUC) in Point-to-Point Microwave
Transmit Systems
• AN-837: DDS-Based Clock Jitter Performance vs. DAC
Reconstruction Filter Performance
• AN-922: Digital Pulse-Shaping Filter Basics
• AN-924: Digital Quadrature Modulator Gain
Data Sheet
• AD9957: 1 GSPS Quadrature Digital Upconverter with 18-
Bit IQ Data Path and 14-Bit DAC Data Sheet
User Guides
• UG-208: Evaluation Board User Guide for AD9957
Tools and Simulations
• AD9957 IBIS Model
Reference Materials
Technical Articles
• Improved DDS Devices Enable Advanced Comm Systems
Design Resources
• AD9957 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9957 EngineerZone Discussions
Sample and Buy
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Technical Support
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AD9957
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 4
Specifications..................................................................................... 5
Electrical Specifications ............................................................... 5
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 12
Modes of Operation ....................................................................... 16
Overview...................................................................................... 16
Quadrature Modulation Mode ................................................. 17
BlackFin Interface (BFI) Mode ................................................. 18
Interpolating DAC Mode .......................................................... 19
Single Tone Mode ....................................................................... 20
Signal Processing ............................................................................ 21
Parallel Data Clock (PDCLK)................................................... 21
Transmit Enable Pin (TxEnable) .............................................. 21
Input Data Assembler ................................................................ 22
Inverse CCI Filter ....................................................................... 23
Fixed Interpolator (4×) .............................................................. 23
Programmable Interpolating Filter .......................................... 24
QDUC Mode........................................................................... 24
RAM Ramp-Up Mode........................................................... 29
RAM Bidirectional Ramp Mode .......................................... 30
RAM Continuous Bidirectional Ramp Mode .................... 32
RAM Continuous Recirculate Mode................................... 33
Clock Input (REF_CLK)................................................................ 34
REFCLK Overview..................................................................... 34
Crystal Driven REF_CLK ......................................................... 34
Direct Driven REF_CLK ........................................................... 34
Phase-Locked Loop (PLL) Multiplier...................................... 35
PLL Charge Pump ...................................................................... 36
External PLL Loop Filter Components ................................... 36
PLL Lock Indication .................................................................. 36
Additional Features ........................................................................ 37
Output Shift Keying (OSK)....................................................... 37
Manual OSK............................................................................ 37
Automatic OSK....................................................................... 37
Profiles ......................................................................................... 38
I/O_UPDATE Pin ...................................................................... 38
Automatic I/O Update ............................................................... 38
Power-Down Control ................................................................ 39
General-Purpose I/O (GPIO) Port .......................................... 39
Synchronization of Multiple Devices........................................... 40
Overview ..................................................................................... 40
Clock Generator ......................................................................... 40
Sync Generator ........................................................................... 40
BFI Mode................................................................................. 24
Quadrature Modulator .............................................................. 25
DDS Core..................................................................................... 25
Inverse Sinc Filter ....................................................................... 25
Output Scale Factor (OSF) ........................................................ 26
14-Bit DAC .................................................................................. 26
Auxiliary DAC ........................................................................ 26
RAM Control .................................................................................. 27
RAM Overview........................................................................... 27
RAM Segment Registers............................................................ 27
RAM State Machine ................................................................... 27
RAM Trigger (RT) Pin............................................................... 27
Load/Retrieve RAM Operation ................................................ 28
RAM Playback Operation ......................................................... 28
Overview of RAM Playback Modes......................................... 29
Sync Receiver .............................................................................. 41
Setup/Hold Validation ............................................................... 42
Synchronization Example ......................................................... 44
I/Q Path Latency......................................................................... 45
Example ................................................................................... 45
Power Supply Partitioning............................................................. 46
3.3 V Supplies.............................................................................. 46
DVDD_I/O (Pin 11, Pin 15, Pin 21, Pin 28, Pin 45, Pin 56,
Pin 66)...................................................................................... 46
AVDD (Pin 74 to Pin 77 and Pin 83) .................................. 46
1.8 V Supplies.............................................................................. 46
DVDD (Pin 17, Pin 23, Pin 30, Pin 47, Pin 57, Pin 64) .... 46
AVDD (Pin 3) ......................................................................... 46
AVDD (Pin 6) ......................................................................... 46
AVDD (Pin 89 and Pin 92) ................................................... 46
Rev. D | Page 2 of 64



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Data Sheet
Serial Programming ........................................................................47
Control Interface—Serial I/O....................................................47
General Serial I/O Operation ....................................................47
Instruction Byte...........................................................................47
Instruction Byte Information Bit Map .................................47
Serial I/O Port Pin Descriptions ...............................................47
SCLK—Serial Clock................................................................47
CS—Chip Select Bar ...............................................................47
SDIO—Serial Data Input/Output .........................................47
SDO—Serial Data Out ...........................................................48
I/O_RESET—Input/Output Reset ........................................48
I/O_UPDATE—Input/Output Update ................................48
Serial I/O Timing Diagrams ......................................................48
MSB/LSB Transfers .....................................................................48
I/O_UPDATE, SYNC_CLK, and System Clock
Relationships................................................................................49
Register Map and Bit Descriptions ...............................................50
Register Map ................................................................................50
AD9957
Register Bit Descriptions............................................................55
Control Function Register 1 (CFR1)....................................55
Control Function Register 2 (CFR2)....................................56
Control Function Register 3 (CFR3)....................................58
Auxiliary DAC Control Register...........................................58
I/O Update Rate Register.......................................................58
RAM Segment Register 0.......................................................58
RAM Segment Register 1.......................................................59
Amplitude Scale Factor (ASF) Register ...............................59
Multichip Sync Register .........................................................59
Profile Registers...........................................................................60
Profile<7:0> Register—Single Tone......................................60
Profile<7:0> Register—QDUC .............................................60
RAM Register ..........................................................................60
GPIO Configuration Register ...............................................60
GPIO Data Register ................................................................60
Outline Dimensions........................................................................61
Ordering Guide ...........................................................................61
Rev. D | Page 3 of 64



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