AD9956 Datasheet PDF - Analog Devices

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AD9956
Analog Devices

Part Number AD9956
Description 2.7 GHz DDS-Based AgileRF
Page 30 Pages


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2.7 GHz DDS-Based AgileRFTM Synthesizer
AD9956
FEATURES
400 MSPS internal DDS clock speed
48-bit frequency tuning word
14-bit programmable phase offset
Integrated 14-bit DAC
Excellent dynamic performance
Phase noise ≤ 135 dBc/Hz @ 1 KHz offset
−80 dB SFDR @ 160 MHz (±100 KHz offset IOUT)
25 Mb/s write-speed serial I/O control
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase
frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 phase/frequency profiles
1.8 V supply for device operation
3.3 V supply for I/O and charge pump
Software controlled power-down
48-lead LFCSP package
Automatic linear frequency sweeping capability (in DDS)
Programmable charge pump current (up to 4 mA)
Phase modulation capability
Multichip synchronization
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant driver
APPLICATIONS
Agile LO frequency synthesis
FM chirp source for radar and scanning systems
Automotive radars
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
DAC_RSET
DELTA
FREQUENCY
TUNING WORD
FREQUENCY
ACCUMULATOR
PLL_LOCK/SYNC_IN
I/O_UPDATE
DELTA
FREQUENCY
24 RAMP RATE
16
48 PHASE
OFFSET
19
FTW
48
PHASE
ACCUMULATOR
PHASE
OFFSET
WORD
14
DDS CORE
PHASE TO
AMPLITUDE
CONVERSION
SYSCLK
TIMING AND CONTROL LOGIC
14
DAC
SYSCLK
IOUT
IOUT
I/O_RESET
SYNC_OUT
REFCLK
REFCLK
SYNC_CLK
RF-DIVIDER
÷R
CML CLOCK DRIVER
SYSCLK
÷4
3
OSCILLATOR
BUFFER
LOCK
DETECT
÷M
Φ
÷N
CHARGE
PUMP
SCALER
3
CHARGE
PUMP
CP_OUT
FROM PLLOSC
BUFFER
DRV DRV DRV_RSET
PS<2:0> RESET I/O PORT PLLREF/ PLLOSC/
PLLREF PLLOSC
Figure 1.
CP_RSET
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.



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AD9956
TABLE OF CONTENTS
Product Overview............................................................................. 3
Specifications..................................................................................... 4
Loop Measurement Conditions.................................................. 9
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Typical Application Circuits.......................................................... 16
Application Circuit Explanations............................................. 17
General Description ....................................................................... 18
DDS Core..................................................................................... 18
PLL Circuitry .............................................................................. 18
REVISION HISTORY
7/04—Revision: Initial Version
CML Driver................................................................................. 19
Modes of Operation ....................................................................... 20
DDS Modes of Operation ......................................................... 20
Synchronization Modes for Multiple Devices.............................. 20
Serial Port Operation ..................................................................... 22
Instruction Byte .......................................................................... 23
Serial Interface Port Pin Description....................................... 23
MSB/LSB Transfers .................................................................... 23
Register Map and Description ...................................................... 24
Control Function Register Descriptions ................................. 27
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 32
Rev. 0 | Page 2 of 32



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PRODUCT OVERVIEW
The AD9956 is Analog Devices’ newest AgileRF synthesizer.
The device is comprised of DDS and PLL circuitry. The DDS
features a 14-bit DAC operating at up to 400 MSPS and a 48-bit
frequency tuning word (FTW). The PLL circuitry includes a
phase frequency detector with scaleable 200 MHz inputs
(divider inputs operate up to 655 MHz) and digital control over
the charge pump current. The device also includes a 655 MHz
CML-mode PECL-compliant driver with programmable slew
rates. The AD9956 uses advanced DDS technology, an internal
high speed, high performance DAC, and an advanced phase
frequency detector/charge pump combination, which, when
used with an external VCO, enables the synthesis of digitally
programmable, frequency-agile analog output sinusoidal wave-
forms up to 2.7 GHz. The AD9956 is designed to provide fast
frequency hopping and fine tuning resolution (48-bit frequency
tuning word). Information is loaded into the AD9956 via a
serial I/O port that has a device write-speed of 25 Mb/s. The
AD9956 DDS block also supports a user-defined linear sweep
mode of operation.
The AD9956 is specified to operate over the extended
automotive range of −40°C to +125°C.
AD9956
Rev. 0 | Page 3 of 32



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AD9956
SPECIFICATIONS
AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ TA = 25°C) DAC_RSET = 3.92 kΩ, CP_RSET = 3.09 kΩ,
DRV_RSET = 4.02 kΩ, unless otherwise noted.
Table 1.
Parameter
RF DIVIDER (REFCLK ) INPUT SECTION (÷R)
RF Divider Input Range
Min
1
Input Capacitance (DC)
Input Impedance (DC)
Input Duty Cycle
Input Power/Sensitivity
Input Voltage Level
PHASE FREQUENCY DETECTOR/CHARGE PUMP
PLLREF Input
Input Frequency2
÷M Set to Divide by at Least 4
÷M Bypassed
Input Voltage Levels
Input Capacitance
Input Resistance
PLLOSC Input
Input Frequency
÷N Set to Divide by at Least 4
÷N Bypassed
Input Voltage Levels
Input Capacitance
Input Resistance
Charge Pump Source/Sink Maximum Current
Charge Pump Source/Sink Accuracy
Charge Pump Source/Sink Matching
Charge Pump Output Compliance Range3
PLL_LOCK Drive Strength
PHASE FREQUENCY DETECTOR NOISE FLOOR
@ 50 kHz PFD Frequency
@ 2 MHz PFD Frequency
@ 100 MHz PFD Frequency
@ 200 MHz PFD Frequency
CML OUTPUT DRIVER (DRV)
Differential Output Voltage Swing4
Maximum Toggle Rate
Common-Mode Output Voltage
Output Duty Cycle
Output Current
Continuous5
Rising Edge Surge
Falling Edge Surge
Output Rise Time
42
−10
350
200
200
−15
−5
0.5
655
42
Typ Max
2700
3
1500
50
58
+4
1000
Unit
MHz
pF
%
dBm
mV p-p
Test Conditions/Comments
DDS SYSCLK not to exceed
400 MSPS
Single-ended, into a 50 Ω load1
450
1500
655
200
600
10
MHz
MHz
mV p-p
pF
450
1500
2
655
200
600
10
4
+5
+5
CP_VDD − 0.5
MHz
MHz
mV p-p
pF
mA
%
%
V
mA
149 dBc/Hz
133 dBc/Hz
116 dBc/Hz
113 dBc/Hz
720
1.75
50 58
mV
MHz
V
%
7.2 mA
20.9 mA
13.5 mA
250 ps
50 Ω load to supply, both lines
100 Ω terminated, 5 pF load
Rev. 0 | Page 4 of 32



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