AD9955 PIN DESCRIPTIONS
Ground Reference Voltage Connection.
Positive voltage power connection, nominally + 5 V.
Buffer Register Clock. Data inputs are loaded into
the Frequency Control Word Buffer Register on the
rising edge of BRCLK when register is enabled
(BREN input at Logic "1").
System Clock. Continuous TTL signal for
synchronizing all internal operations, except loading
of Frequency Control Word Buffer Register; rising
edge initiates synchronization.
F[0:31] 32 parallel data inputs for loading frequency tuning
Buffer Load Enable Signal. Enables loading of data
into the Frequency Control Word Buffer Register.
If BREN is logic "0," register retains its contents. If
BREN is Logic "1," theFrequency Control Word
Buffer Register either (1) parallel loads the data
present at F[0:31] inputs (PSEL = HIGH) or (2)
serially shifts data present at F input (PSEL =
FCLD Frequency Control Load Enable Signal. FCLD =
HIGH enables loading of data from Frequency
Control Word Buffer Register into Frequency
Control Register. Loading takes place on next rising
edge of CLK signal. FCLD = LOW disables
loading of data.
Data Ready Signal. Output data (SIN [0: 11]) is
valid on the rising edge of DRDY, which tracks
propagation delay variations of the output data vs.
temperature. The duty cycle of DRDY is dependent
on the duty cycle of the CLK input. The DRDY
signal should be used only for applications which
have a very high clock rate (85 Msps) and require
operation over a wide temperature range. Normally
allowed to float.
CIN Carry-In signal is provided as the carry input to the
least significant bit (LSB) of the 32-bit adder in the
phase accumulator. This signal is used as the carry
input only if the TGLE signal is a logic zero; carry
has 1 LSB weight, and is used for stacking units for
64-bit DDS. Normally tied to ground.
Carry Toggle Enable. When HIGH, the CIN signal
is disabled, and the Carry-In toggles internally
between HIGH and LOW on each clock (CLK)
cycle to reduce the worst case spurious response of
the digital output signal by 3.92 dB. Normally tied
Twos Complement/Magnitude Mode Select. Selects
binary output format of data on SIN[O:11] outputs.
If TCMS is a Logic "1," format of output data at
SIN[O:11] is in twos complement format. If TCMS
is a Logic "0," data is binary unsigned magnitude
format. Normally tied to ground.
SIN[O:11] 12 parallel data bits comprising the sine data output.
Frequency of the sine data outputs is defined by the
Frequency Control Register (~ phase) as
( )~ PhaSe
louT = !eLK ~
Binary data format of 12-bit samples is either twos
complement or unsigned magnitude, determined by
Reset Phase to Zero Signal. Activates synchronous
reset of the Phase Accumulation Register to a
binary value of "0," or zero radians. Reset is
enabled when RSTO is a Logic "1" and takes place
on rising edge of system clock (CLK). Normally
Carry-Out signal output of the 32-bit adder in the
phase accumulator; used for stacking two AD9955
units for 64-bit DDS. Normally allowed to float.
ParalleUSerial Frequency Control Word Buffer
Input Selector. Selects mode for loading the Buffer
Register. If a load is enabled (BREN = "1"), and
PSEL is a Logic "1," data is parallel loaded into the
Frequency Control Word Buffer Register from the
FO:31] inputs on the next rising edge of BRCLK. If
a load is enabled and PSEL is a Logic "0," data is
serially shifted into the Frequency Control Word
Buffer Register from the F input on rising edge of
41 I TGlE
~ [ ~ ~ E ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~ ~
Datasheet pdf - http://www.DataSheet4U.net/