AD9739A Datasheet PDF - Analog Devices

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AD9739A
Analog Devices

Part Number AD9739A
Description RF Digital-to-Analog Converters
Page 30 Pages


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Data Sheet
11-/14-Bit, 2.5 GSPS,
RF Digital-to-Analog Converters
AD9737A/AD9739A
FEATURES
Direct RF synthesis at 2.5 GSPS update rate
DC to 1.25 GHz in baseband mode
1.25 GHz to 3.0 GHz in mix-mode
Industry leading single/multicarrier IF or RF synthesis
Dual-port LVDS data interface
Up to 1.25 GSPS operation
Source synchronous DDR clocking
Pin compatible with the AD9739
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.1 W at 2.5 GSPS
APPLICATIONS
Broadband communications systems
DOCSIS CMTS systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics
SDIO
SDO
CS
SCLK
FUNCTIONAL BLOCK DIAGRAM
RESET
IRQ
AD9737A/AD9739A
1.2V
SPI
DAC BIAS
VREF
I120
IOUTN
DCI
TxDAC
CORE
IOUTP
DCO
CLK DISTRIBUTION
(DIV-BY-4)
DLL
(MU CONTROLLER)
GENERAL DESCRIPTION
The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high
performance RF DACs that are capable of synthesizing wideband
signals from dc up to 3 GHz. The AD9737A/AD9739A are pin
and functionally compatible with the AD9739 with the
exception that the AD9737A/AD9739A do not support
synchronization or RZ mode, and are specified to operate
between 1.6 GSPS and 2.5 GSPS.
By elimination of the synchronization circuitry, some nonideal
artifacts such as images and discrete clock spurs remain stationary
on the AD9737A/AD9739A between power-up cycles, thus
allowing for possible system calibration. AC linearity and noise
performance remain the same between the AD9739 and the
AD9737A/AD9739A.
The inclusion of on-chip controllers simplifies system integration.
A dual-port, source synchronous, LVDS interface simplifies the
digital interface with existing FGPA/ASIC technology. On-chip
controllers are used to manage external and internal clock domain
variations over temperature to ensure reliable data transfer from
the host to the DAC core. A serial peripheral interface (SPI) is
used for device configuration as well as readback of status
registers.
Figure 1.
DACCLK
The AD9737A/AD9739A are manufactured on a 0.18 µm
CMOS process and operate from 1.8 V and 3.3 V supplies.
They are supplied in a 160-ball chip scale ball grid array for
reduced package parasitics.
PRODUCT HIGHLIGHTS
1. Ability to synthesize high quality wideband signals with
bandwidths of up to 1.25 GHz in the first or second
Nyquist zone.
2. A proprietary quad-switch DAC architecture provides
exceptional ac linearity performance while enabling mix-
mode operation.
3. A dual-port, double data rate, LVDS interface supports the
maximum conversion rate of 2500 MSPS.
4. On-chip controllers manage external and internal clock
domain skews.
5. Programmable differential current output with an 8.66 mA
to 31.66 mA range.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved.



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AD9737A/AD9739A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
LVDS Digital Specifications ........................................................ 5
Serial Port Specifications ............................................................. 6
AC Specifications.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics—AD9737A ..................... 14
Static Linearity ............................................................................ 14
AC (Normal Mode).................................................................... 15
AC (Mix-Mode).......................................................................... 17
One-Carrier DOCSIS Performance (Normal Mode) ............ 20
Four-Carrier DOCSIS Performance (Normal Mode) ........... 21
Eight-Carrier DOCSIS Performance (Normal Mode) .......... 22
16-Carrier DOCSIS Performance (Normal Mode) ............... 23
32-Carrier DOCSIS Performance (Normal Mode) ............... 24
64- and 128-Carrier DOCSIS Performance (Normal Mode)25
Typical Performance Characteristics—AD9739A ..................... 26
Static Linearity ............................................................................ 26
AC (Normal Mode).................................................................... 28
AC (Mix-Mode).......................................................................... 31
One-Carrier DOCSIS Performance (Normal Mode) ............ 33
Four-Carrier DOCSIS Performance (Normal Mode) ........... 34
Eight-Carrier DOCSIS Performance (Normal Mode) .......... 35
16-Carrier DOCSIS Performance (Normal Mode) ............... 36
32-Carrier DOCSIS Performance (Normal Mode) ............... 37
64- and 128-Carrier DOCSIS Performance (Normal Mode)38
Terminology .................................................................................... 39
Serial Port Interface (SPI) Register............................................... 40
Data Sheet
SPI Register Map Description .................................................. 40
SPI Operation ............................................................................. 40
SPI Register Map ............................................................................ 42
SPI Port Configuration and Software Reset ........................... 43
Power-Down LVDS Interface and TxDAC® ........................... 43
Controller Clock Disable........................................................... 43
Interrupt Request (IRQ) Enable/Status ................................... 44
TxDAC Full-Scale Current Setting (IOUTFS) and Sleep ........... 44
TxDAC Quad-Switch Mode of Operation.............................. 44
DCI Phase Alignment Status .................................................... 44
Data Receiver Controller Configuration................................. 44
Data Receiver Controller_Data Sample Delay Value ............ 45
Data Receiver Controller_DCI Delay Value/Window and
Phase Rotation ............................................................................ 45
Data Receiver Controller_Delay Line Status .......................... 45
Data Receiver Controller Lock/Tracking Status..................... 45
CLK Input Common Mode ...................................................... 46
Mu Controller Configuration and Status................................ 46
Part ID ......................................................................................... 47
Theory of Operation ...................................................................... 48
LVDS Data Port Interface.......................................................... 49
Mu Controller ............................................................................. 52
Interrupt Requests...................................................................... 54
Analog Interface Considerations.................................................. 55
Analog Modes of Operation ..................................................... 55
Clock Input Considerations...................................................... 56
Voltage Reference ....................................................................... 57
Analog Outputs .......................................................................... 57
Output Stage Configuration ..................................................... 59
Nonideal Spectral Artifacts....................................................... 60
Lab Evaluation of the AD9737A/AD9739A ........................... 61
Recommended Start-Up Sequence .......................................... 61
Outline Dimensions ....................................................................... 63
Ordering Guide .......................................................................... 63
Rev.C | Page 2 of 64



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Data Sheet
REVISION HISTORY
2/12—Rev. B to Rev. C
Changes to Figure 5...........................................................................9
Changes to Table 7 ..........................................................................11
Changes to Ordering Guide...........................................................63
2/12—Rev. A to Rev. B
Added AD9737A ................................................................ Universal
Reorganized Layout ........................................................... Universal
Moved Revision History Section.....................................................3
Deleted ±6% from Table Summary Statement; Changes
to Table 1 ............................................................................................4
Deleted ±6% from Table Summary Statement, Table 2................5
Deleted ±6% from Table Summary Statement, Table 3................6
Changes to AC Specifications Section and Table 4.......................7
Added Figure 5, Renumbered Sequentially ...................................9
Added Figure 7 and Table 7, Renumbered Sequentially ............10
Deleted Figure 24 ............................................................................13
Added Typical Performance Characteristics—AD9737A
Section and Figure 9 to Figure 77 .................................................14
Deleted Table 9 ................................................................................25
Added Static Linearity Section and Figure 78 to Figure 88 ............26
Added Figure 106 ............................................................................30
Changes to Figure 116, Figure 117, Figure 118, Figure 119,
Figure 120, and Figure 121.............................................................33
Changes to Figure 122, Figure 123, Figure 124, Figure 125,
Figure 126, and Figure 127.............................................................34
Changes to Figure 128, Figure 129, Figure 130, Figure 131,
Figure 132, and Figure 133.............................................................35
Changes to Figure 134, Figure 135, Figure 136, Figure 137,
Figure 138, and Figure 139.............................................................36
Changes to Figure 140, Figure 141, Figure 142, Figure 143,
Figure 144, and Figure 145.............................................................37
Changes to Figure 146, Figure 147, Figure 148, Figure 149,
and Figure 150; Added Figure 151 ................................................38
Added Table 10 ................................................................................42
AD9737A/AD9739A
Added SPI Port Configuration and Software Reset Section,
Power-Down LVDS Interface and TxDAC Section, Controller
Clock Disable Section, and Table 11 to Table 13 ........................43
Added Interrupt Request (IRQ) Enable/Status Section, TxDAC
Full-Scale Current Setting (IOUTFS) and Sleep Section, TxDAC
Quad-Switch Mode of Operation Section, DCI Phase
Alignment Status Section, Data Receiver Controller
Configuration Section, and Table 14 to Table 18........................44
Added Data Receiver Controller_Data Sample Delay Value
Section, Data Receiver Controller_DCI Delay Value/Window
and Phase Rotation Section, Data Receiver Controller_Delay
Line Status Section, Data Receiver Controller Lock/Tracking
Status Section, and Table 19 to Table 22 ......................................45
Added CLK Input Common Mode Section, and Mu
Controller Configuration and Status Section, and Table 23
and Table 24 .....................................................................................46
Added Part ID Section, and Table 25 ...........................................47
Changes to LVDS Data Port Interface Section............................49
Changes to Data Receiver Controller Initialization
Description Section ........................................................................51
Changes to Mu Controller Section ...............................................52
Added Figure 167 and Table 27, Changes to Mu Controller
Initialization Description Section.................................................53
Changes to Analog Modes of Operation Section, Figure 171,
and Figure 172 .................................................................................55
Updated Outline Dimensions........................................................63
Changes to Ordering Guide...........................................................63
7/11—Rev. 0 to Rev. A
Changed Maximum Update Rate (DACCLK Input) Parameter
to DAC Clock Rate Parameter in Table 4.......................................6
Added Adjusted DAC Update Rate Parameter and Endnote 1 in
Table 4.................................................................................................6
Updated Outline Dimensions........................................................43
1/11—Revision 0: Initial Version
Rev. C | Page 3 of 64



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AD9737A/AD9739A
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA.
Table 1.
Parameter
RESOLUTION
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Gain Error (with Internal Reference)
Full-Scale Output Current
Output Compliance Range
Common-Mode Output Resistance
Differential Output Resistance
Output Capacitance
DAC CLOCK INPUT (DACCLK_P, DACCLK_N)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Clock Rate
TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
VDDA
VDDC
DIGITAL SUPPLY VOLTAGES
VDD33
VDD
SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS
IVDDA
IVDDC
IVDD33
IVDD
Power Dissipation
Sleep Mode, IVDDA
Power-Down Mode (All Power-Down Bits Set in Register 0x01 and
Register 0x02)
IVDDA
IVDDC
IVDD33
IVDD
SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS
IVDDC
IVDD33
IVDD
Power Dissipation
AD9737A
Min Typ Max
11
AD9739A
Min Typ Max
14
Unit
Bits
±0.5 ±2.5 LSB
±0.5 ±2.0 LSB
5.5 5.5 %
8.66 20.2 31.66 8.66 20.2 31.66 mA
−1.0 +1.0 −1.0 +1.0 V
10 10 MΩ
70 70 Ω
1 1 pF
1.2 1.6 2.0 1.2 1.6 2.0 V
900 900 mV
1.6 2.5 1.6 2.5 GHz
60 60 ppm/°C
20 20 ppm/°C
1.15 1.2
5
1.25 1.15 1.2
5
1.25 V
kΩ
3.1 3.3
1.70 1.8
3.5 3.1 3.3
1.90 1.70 1.8
3.5 V
1.90 V
3.10 3.3
1.70 1.8
3.5 3.10 3.3
1.90 1.70 1.8
3.5 V
1.90 V
37
158
14.5
173
0.770
2.5
38
167
16
183
2.75
37
158
14.5
173
0.770
2.5
38
167
16
183
2.75
mA
mA
mA
mA
W
mA
0.02
6
0.6
0.1
223
14.5
215
0.960
0.02
6
0.6
0.1
223
14.5
215
0.960
mA
mA
mA
mA
mA
mA
mA
mW
Rev.C | Page 4 of 64



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