AD774B Datasheet PDF - Analog Devices

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AD774B
Analog Devices

Part Number AD774B
Description Complete 12-Bit A/D Converters
Page 12 Pages


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a
FEATURES
Complete Monolithic 12-Bit A/D Converters with
Reference, Clock, and Three-State Output Buffers
Industry Standard Pinout
High Speed Upgrades for AD574A
8- and 16-Bit Microprocessor Interface
8 s (Max) Conversion Time (AD774B)
15 s (Max) Conversion Time (AD674B)
؎5 V, ؎10 V, 0 V–10 V, 0 V–20 V Input Ranges
Commercial, Industrial, and Military Temperature
Range Grades
MIL-STD-883-Compliant Versions Available
Complete 12-Bit
A/D Converters
AD674B /AD774B
FUNCTIONAL BLOCK DIAGRAM
5V SUPPLY
VLOGIC
DATA MODE SELECT
12/8
CHIP SELECT
CS
BYTE ADDRESS/
SHORT CYCLE A0
READ/CONVERT R/C
1
2
3
4
5
CHIP ENABLE
CE 6
12V/15V SUPPLY
VCC
10V REFERENCE
REF OUT
7
8
ANALOG COMMON
AC
9
REFERENCE INPUT
REF IN
10
–12V/–15V SUPPLY
VEE 11
BIPOLAR OFFSET
BIPOFF
12
10V SPAN INPUT
10VIN 13
20V SPAN INPUT
20VIN
14
CONTROL
CLOCK
SAR 12
10V
REF
COMP
+
I DAC
MSB
N
Y
3
B
B
S
T
L
E
A
T
A
EN
Y
OB
UB
TL
PE
U
TB
199.95
k
I REF
+
DAC
N
VEE
BN
UY
FB
FB
EL
RE
S
C
LSB
VOLTAGE
DIVIDER AD674B/AD774B
28
STATUS
STS
27 DB11 (MSB)
26 DB10
25 DB9
24 DB8
23 DB7
22 DB6
21 DB5
20 DB4
19 DB3
18 DB2
17 DB1
16 DB0 (LSB)
15
DIGITAL
COMMON DC
DIGITAL
DATA
OUTPUTS
PRODUCT DESCRIPTION
The AD674B and AD774B are complete 12-bit successive-
approximation analog-to-digital converters with three-state
output buffer circuitry for direct interface to 8- and 16-bit
microprocessor busses. A high-precision voltage reference and
clock are included on chip, and the circuit requires only power
supplies and control signals for operation.
The AD674B and AD774B are pin-compatible with the indus-
try standard AD574A, but offer faster conversion time and bus-
access speed than the AD574A and lower power consumption.
The AD674B converts in 15 µs (maximum) and the AD774B
converts in 8 µs (maximum).
The monolithic design is implemented using Analog Devices’
BiMOS II process allowing high-performance bipolar analog
circuitry to be combined on the same die with digital CMOS logic.
Offset, linearity, and scaling errors are minimized by active
laser trimming of thin-film resistors.
Five different grades are available. The J and K grades are
specified for operation over the 0°C to 70°C temperature range.
The A and B grades are specified from –40°C to +85°C, the T grade
is specified from –55°C to +125°C. The J and K grades are
available in a 28-lead plastic DIP or 28-lead SOIC. All other grades
are available in a 28-lead hermetically sealed ceramic DIP.
PRODUCT HIGHLIGHTS
1. Industry Standard Pinout: The AD674B and AD774B use
the pinout established by the industry standard AD574A.
2. Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges: 0 V to
10 V and 0 V to 20 V unipolar; –5 V to +5 V and –10 V to
+10 V bipolar. The AD674B and AD774B operate on +5 V
and ± 12 V or ± 15 V power supplies.
3. Flexible Digital Interface: On-chip multiple-mode three-state
output buffers and interface logic allow direct connection to
most microprocessors. The 12 bits of output data can be
read either as one 12-bit word or as two 8-bit bytes (one with
8 data bits, the other with 4 data bits and 4 trailing zeros).
4. The internal reference is trimmed to 10.00 V with 1% maxi-
mum error and 10 ppm/°C typical temperature coefficient.
The reference is available externally and can drive up to
2.0 mA beyond the requirements of the converter and bipo-
lar offset resistors.
5. The AD674B and AD774B are available in versions compli-
ant with MIL-STD-883. Refer to the Analog Devices Mili-
tary Products Databook or current AD674B/AD774B/883B
data sheet for detailed specifications.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002



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AD674B/AD774B–SPECIFICATIONS (TMIN to TMAX with VCC = +15 V ؎ 10% or +12 V ؎ 5%,
VLOGIC = +5 V ؎ 10%, VEE = –15 V ؎ 10% or –12 V ؎ 5%, unless otherwise noted.)
Model (AD674B or AD774B)
J Grade
K Grade
A Grade
B Grade
T Grade
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Unit
RESOLUTION
12 12 12 12 12
LINEARITY ERROR @ 25°C
TMIN to TMAX
DIFFERENTIAL LINEARITY ERROR
(Minimum Resolution for Which No
Missing Codes are Guaranteed)
12
؎1
؎1
12
؎1/2
؎1/2
12
؎1
؎1
12
؎1/2
؎1/2
12
؎1/2
؎1
UNIPOLAR OFFSET1 @ 25°C
BIPOLAR OFFSET1 @ 25°C
؎2 ؎2 ؎2 ؎2 ؎2
؎6 ؎3 ؎6 ؎3 ؎3
FULL-SCALE CALIBRATION ERROR1, 2
@ 25°C (with Fixed 50 Resistor
from REF OUT to REF IN)
0.1 0.25
0.1 0.125
0.1 0.25
0.1 0.125
0.1 0.125
TEMPERATURE RANGE
TEMPERATURE DRIFT3
(Using Internal Reference)
Unipolar
Bipolar Offset
Full-Scale Calibration
0
70 0
70 –40
+85 –40
+85 –55
+125
؎2 ؎1 ؎2
؎2 ؎1 ؎2
؎6 ؎2 ؎8
؎1 ؎1
؎1 ؎2
؎5 ؎7
POWER SUPPLY REJECTION
Max Change in Full-Scale Calibration
VCC = +15 V ± 1.5 V or +12 V ± 0.6 V
VLOGIC = +5 V ± 0.5 V
VEE = –15 V ± 1.5 V or –12 V ± 0.6 V
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 V Span
20 V Span
–5
–10
0
0
35
6 10
؎2
؎1/2
؎2
؎1
؎1/2
؎1
+5 –5
+10 –10
10 0
20 0
+5 –5
+10 –10
10 0
20 0
73
14 6
57
10 14
3
6
؎2
؎1/2
؎2
+5
+10
10
20
57
10 14
؎1
؎1/2
؎1
–5 +5 –5
–10 +10 –10
0 10 0
0 20 0
3 57
3
6 10 14 6
؎1
؎1/2
؎1
+5
+10
10
20
57
10 14
POWER SUPPLIES
Operating Range
VLOGIC
VCC
VEE
Operating Current
ILOGIC
ICC
IEE
POWER CONSUMPTION
4.5
11.4
–16.5
5.5 4.5
16.5 11.4
–11.4 –16.5
5.5 4.5
16.5 11.4
–11.4 –16.5
5.5
16.5
–11.4
4.5
11.4
–16.5
5.5 4.5
16.5 11.4
–11.4 –16.5
5.5
16.5
–11.4
3.5 7
3.5 7
10 14
220 375
175
3.5 7
3.5 7
10 14
220 375
175
3.5 7
3.5 7
10 14
220 375
175
3.5 7
3.5 7
10 14
220 375
175
3.5 7
3.5 7
10 14
220 375
175
INTERNAL REFERENCE VOLTAGE
Output Current
(Available for External Loads)
(External Load Should Not
Change During the Conversion)
9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1
2.0 2.0 2.0 2.0 2.0
Bits
LSB
LSB
Bits
LSB
LSB
% of FS
°C
LSB
LSB
LSB
LSB
LSB
LSB
V
V
V
V
k
k
V
V
V
mA
mA
mA
mW4
mW5
V
mA
NOTES
1Adjustable to zero.
2Includes internal voltage reference error.
3Maximum change from 25°C value to the value at TMIN or TMAX.
4Tested with REF OUT tied to REF IN through 50 resistor, VCC = +16.5 V, VEE = –16.5 V, VLOGIC = +5.5 V, and outputs in high-Z mode.
5Tested with REF OUT tied to REF IN through 50 resistor, VCC = +12 V, VEE = –12 V, VLOGIC = +5 V, and outputs in high-Z mode.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at TMIN, 25°C, and TMAX. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed, although only those shown in boldface are tested.
–2– REV. C



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AD674B/AD774B
DIGITAL SPECIFICATIONS (For all grades TMIN to TMAX with VCC = +15 V ؎ 10% or +12 V ؎ 5%, VLOGIC = +5 V ؎ 10%,
VEE = –15 V ؎ 10% or –12 V ؎ 5%, unless otherwise noted.)
Parameter
Test Conditions
Min
Max Unit
LOGIC INPUTS
VIH High Level Input Voltage
VIL Low Level Input Voltage
IIH High Level Input Current
IIL Low Level Input Current
CIN Input Capacitance
VIN = VLOGIC
VIN = 0 V
2.0
–0.5
–10
–10
VLOGIC + 0.5
+0.8
+10
+10
10
V
V
µA
µA
pF
LOGIC OUTPUTS
VOH High Level Output Voltage
VOL Low Level Output Voltage
IOZ High-Z Leakage Current
COZ High-Z Output Capacitance
IOH = 0.5 mA
IOL = 1.6 mA
VIN = 0 to VLOGIC
2.4
–10
V
0.4 V
+10 µA
10 pF
SWITCHING SPECIFICATIONS (For all grades TMIN to TMAX with VCC = +15 V ؎ 10% or +12 V ؎ 5%,
VLOGIC = +5 V ؎ 10%, VEE = –15 V ؎ 10% or –12 V ؎ 5%, unless otherwise noted.)
CONVERTER START TIMING (Figure 1)
Parameter
J, K, A, B Grades T Grade
Symbol Min Typ Max Min Typ Max Unit
Conversion Time
8-Bit Cycle (AD674B) tC
12-Bit Cycle (AD674B) tC
8-Bit Cycle (AD774B) tC
12-Bit Cycle (AD774B) tC
STS Delay from CE
tDSC
CE Pulsewidth
tHEC
CS to CE Setup
tSSC
CS Low During CE High tHSC
R/C to CE Setup
tSRC
R/C LOW During CE High tHRC
A0 to CE Setup
tSAC
A0 Valid During CE High tHAC
6 8 10 6 8 10 µs
9 12 15 9 12 15 µs
4 5 6 4 5 6 µs
6 7.3 8 6 7.3 8 µs
200 225 ns
50 50 ns
50 50 ns
50 50 ns
50 50 ns
50 50 ns
0 0 ns
50 50 ns
READ TIMING—FULL CONTROL MODE (Figure 2)
Parameter
J, K, A, B Grades T Grade
Symbol Min Typ Max Min Typ Max Unit
Access Time
CL = 100 pF
Data Valid After CE Low
tDD1
tHD
Output Float Delay
CS to CE Setup
R/C to CE Setup
A0 to CE Setup
CS Valid After CE Low
R/C High After CE Low
A0 Valid After CE Low
tHL5
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
75 150
75 150 ns
252 252 ns
203 154 ns
150 150 ns
50 50 ns
0 0 ns
50 50 ns
0 0 ns
0 0 ns
50 50 ns
NOTES
1tDD is measured with the load circuit of Figure 3a and is defined as the time required
for an output to cross 0.4 V or 2.4 V.
20°C to TMAX.
3At –40°C.
4At –55°C.
5tHL is defined as the time required for the data lines to change 0.5 V when loaded with
the circuit of Figure 3b.
Specifications shown in boldface are tested on all devices at final electrical test with
worst case supply voltages at TMIN, 25°C, and TMAX. Results from those tests are used
to calculate outgoing quality levels. All min and max specifications are guaranteed,
although only those shown in boldface are tested.
Specifications subject to change without notice.
REV. C
–3–
CE tHEC
CS
tSSC
tHSC
tSRC tHRC
R/C
A0 tHAC
tSAC
STS
DB11 DB0
tDSC
tC
HIGH
IMPEDANCE
Figure 1. Convert Start Timing
CE
tSSR
CS
tHSR
R/C tSRR
tHRR
A0 tSAR
tHAR
STS
DB11 DB0
tHD
HIGH
IMPEDANCE
tDD
DATA
VALID
tHL
Figure 2. Read Cycle Timing
5V
HIGH
IMPEDANCE
DBN
3k
100pF
DBN
3k
100pF
HIGH-Z TO LOGIC 1
High-Z to Logic 1
HIGH-Z TO LOGIC 0
High-Z to Logic 0
Figure 3a. Load Circuit for Access Time Test
5V
DBN
3k
100pF
DBN
3k
100pF
LOGIC 1 TO HIGH-Z
LOGIC 0 TO HIGH-Z
Logic 1 to High-Z
Logic 0 to High-Z
Figure 3b. Load Circuit for Output Float Delay Test



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AD674B/AD774B
TIMING—STAND ALONE MODE (Figures 4a and 4b)
tHRL
Parameter
J, K, A, B Grades T Grade
Symbol Min Typ Max Min Typ Max Unit
R/C
Data Access Time
Low R/C Pulsewidth
tDDR
tHRL
STS Delay from R/C
tDS
Data Valid After R/C Low tHDR
STS Delay After Data Valid tHS
High R/C Pulsewidth
tHRH
150
50
200
25
30 200 600
150
Specifications subject to change without notice.
150
50
225
25
30 200 600
150
ns
ns
ns
ns
ns
ns
STS
DB11DB0
DATA
VALID
tDS
tHDR
tC
HIGHZ
tHS
DATA VALID
ABSOLUTE MAXIMUM RATINGS*
VCC to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +16.5 V
VEE to Digital Common . . . . . . . . . . . . . . . . . . . . 0 to 16.5 V
VLOGIC to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +7 V
Analog Common to Digital Common . . . . . . . . . . . . . . . ± 1 V
Digital Inputs to Digital Common . . . 0.5 V to VLOGIC +0.5 V
Analog Inputs to Analog Common . . . . . . . . . . . . VEE to VCC
20 VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . ± 24 V
REF OUT . . . . . . . . . . . . . . . . . . Indefinite Short to Common
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to VCC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Flgure 4a. Standalone Mode Timing Low Pulse R/C
R/C
STS
tHRH
tDS
tDDR
tHDR
tC
DB11DB0 HIGHZ
DATA
VALID
HIGHZ
tHL
Figure 4b. Standalone Mode Timing High Pulse for R/C
ORDERING GUIDE
Modell
AD674BJN
AD674BKN
AD674BAR
AD674BBR
AD674BAD
AD674BBD
AD674BTD
AD774BJN
AD774BKN
AD774BAR
AD774BBR
AD774BAD
AD774BBD
AD774BTD
Temperature
0°C to 70°C
0°C to 70°C
40°C to +85°C
40°C to +85°C
40°C to +85°C
40°C to +85°C
55°C to +125°C
0°C to 70°C
0°C to 70°C
40°C to +85°C
40°C to +85°C
40°C to +85°C
40°C to +85°C
55°C to +125°C
Conversion
Time (max)
15 µs
15 µs
15 µs
15 µs
15 µs
15 µs
15 µs
8 µs
8 µs
8 µs
8 µs
8 µs
8 µs
8 µs
INL
(TMIN to TMAX)
± 1 LSB
± 1/2 LSB
± 1 LSB
± 1/2 LSB
± 1 LSB
± 1/2 LSB
± 1 LSB
± 1 LSB
± 1/2 LSB
± 1 LSB
± 1/2 LSB
± 1 LSB
± 1/2 LSB
± 1 LSB
Package
Description
Plastic DIP
Plastic DIP
Plastic SOIC
Plastic SOIC
Ceramic DIP
Ceramic DIP
Ceramic DIP
Plastic DIP
Plastic DIP
Plastic SOIC
Plastic SOIC
Ceramic DIP
Ceramic DIP
Ceramic DIP
Package
Option2
N-28
N-28
R-28
R-28
D-28
D-28
D-28
N-28
N-28
R-28
R-28
D-28
D-28
D-28
NOTES
1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military
Products Databook or the current AD674B/ AD774B/883B data sheet.
2N = Plastic DIP; D = Hermetic DIP; R = Plastic SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD674B/AD774B features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. C



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