1/4- to 1/12 Duty VFD Controller/Driver
Grid1 to Grid4
LED1 to LED4
High-voltage output (Segment)
High-voltage output (Grid)
Key data input
Input serial data at rising edge of shift clock,
starting from the low order bit.
Output serial data at the falling edge of the
6 shift clock, starting from low order bit. This is
N-ch open-drain output pin.
Initializes serial interface at the rising or
falling edge of the AD6315. It then waits for
reception of a command. Data input after
STB falling is processed as a command.
While command data is processed, current
processing is stopped, and the serial
interface is initialized. While STB is high, CLK
Reads serial data at the rising edge, and
outputs data at the falling edge.
Connect resistor in between this pin and Vss to set
up the oscillation frequency.
14 to 29
Segment output pins (Dual function as key
39 to 42 Grid output pins
31 to 38
These pins are selectable for segment or grid
1 to 4 CMOS output
Data input to these pins is latched at the end
of the display cycle.
13, 43 Logic power supply
12, 44 Connect this pin to system GND.
30 Driver power supply
AD6315X X X
L : LQFP-44L
F: Lead Free
Blank : Tray
Rev. A5 Dec 29, 2003