AD1376 Datasheet PDF - Analog Devices

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AD1376
Analog Devices

Part Number AD1376
Description High Speed 16-Bit A/D Converters
Page 12 Pages


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Complete, High Speed
16-Bit A/D Converters
AD1376/AD1377
FEATURES
Complete 16-bit converters with reference and clock
±0.003% maximum nonlinearity
Digital output data is provided in parallel form with
corresponding clock and status outputs. All digital inputs and
outputs are TTL-compatible.
No missing codes to 14 bits over temperature
Fast conversion
17 µs to 16 bits (AD1376)
10 µs to 16 bits (AD1377)
Short cycle capability
Adjustable clock rate
Parallel outputs
For the AD1376, the serial output function is no longer
available after date code 0111. For the AD1377, the serial output
function is no longer available after date code 0210. The option
of applying an external clock on the CONVERT START pin to
slow down the internally set conversion time is no longer
supported for either part.
Low power
645 mW typical (AD1376)
585 mW typical (AD1377)
Industry-standard pinout
PRODUCT HIGHLIGHTS
1. The AD1376/AD1377 provide 16-bit resolution with a
maximum linearity error of ±0.003% (1/2 LSB14) at 25°C.
GENERAL DESCRIPTION
The AD1376/AD1377 are high resolution, 16-bit analog-to-
digital converters with internal reference, clock, and laser-
trimmed thin-film applications resistors. The AD1376/AD1377
are excellent for use in high resolution applications requiring
moderate speed and high accuracy or stability over commercial
temperature ranges (0°C to 70°C). They are packaged in
compact 32-lead, ceramic seam-sealed (hermetic), dual in-line
packages (DIP). Thin-film scaling resistors provide bipolar
input ranges of ±2.5 V, ±5 V, and ±10 V and unipolar input
ranges of 0 V to +5 V, 0 V to +10 V, and 0 V to +20 V.
2. The AD1376 conversion time is 14 µs (typical) short cycled
to 14 bits, and 16 µs to 16 bits.
3. The AD1377 conversion time is 8 µs (typical) short cycled
to 14 bits, and 9 µs to 16 bits.
4. Two binary codes are available on the digital output. They
are CSB (complementary straight binary) for unipolar input
voltage ranges and COB (complementary offset binary) for
bipolar input ranges. Complementary twos complement
(CTC) coding may be obtained by inverting Pin 1 (MSB).
5. The AD1376/AD1377 include internal reference and clock
with external clock rate adjust pin, and parallel digital outputs.
FUNCTIONAL BLOCK DIAGRAM
(MSB) BIT 1 1
BIT 2 2
BIT 3 3
BIT 4 4
BIT 5 5
BIT 6 6
BIT 7 7
BIT 8 8
BIT 9 9
BIT 10 10
BIT 11 11
BIT 12 12
(LSB FOR 13 BITS) BIT 13 13
(LSB FOR 14 BITS) BIT 14 14
BIT 15 15
BIT 16 16
AD1376/AD1377
16-BIT SAR
COMPARATOR
32 SHORT CYCLE
31 CONVERT START
REFERENCE
30 +5V DC SUPPLY VL
29 GAIN ADJUST
7.5k
28 +15V DC SUPPLY VCC
27 COMPARATOR IN
26 BIPOLAR OFFSET
25 +10V
3.75k3.75k
24 +20V
23 CLK RATE CTRL
22 ANALOG COMMON
21 –15V DC SUPPLY VEE
20 CLOCK OUT
CLOCK
19 DIGITAL COMMON
18 STATUS
17 NC
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.481.3113 © 2005 Analog Devices, Inc. All rights reserved.



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AD1376/AD1377
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Description of Operation ................................................................ 6
Gain Adjustment .......................................................................... 6
Zero Offset Adjustment............................................................... 6
Timing............................................................................................ 7
Digital Output Data ..................................................................... 7
REVISION HISTORY
6/05—Rev. C to Rev. D
Updated Format..................................................................Universal
Updated Outline Dimensions ....................................................... 12
6/03—Rev. B to Rev. C
Removed Serial Output Function and
Adjustable Clock Rate ........................................................Universal
Updated Format..................................................................Universal
Changes to General Description .................................................... 1
Changes to Product Highlights....................................................... 1
Changes to Functional Block Diagram.......................................... 1
Inserted ESD Warning ..................................................................... 3
Change to Ordering Guide.............................................................. 3
Change to Figure 7 ........................................................................... 5
Deleted text from Digital Output Data.......................................... 5
Deleted Figure 9 and Renumbered Remainder of Figures.......... 5
Deleted the ‘Using the AD1376 or AD1377 at
Slower Conversion Times’ Section ............................................... 8
Deleted Figure 16.............................................................................. 8
Change to Figure 13 ......................................................................... 9
Change to Figure 14 ......................................................................... 9
Updated Outline Dimensions ....................................................... 10
Input Scaling ..................................................................................7
Calibration (14-Bit Resolution Examples) .................................8
Grounding, Decoupling, and Layout Considerations ..............9
Clock Rate Control........................................................................9
High Resolution Data Acquisition System.............................. 10
Applications..................................................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
Rev. D | Page 2 of 12



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AD1376/AD1377
SPECIFICATIONS
Typical at TA = 25°C, VS = ±15 V, +5 V, unless otherwise noted.
Table 1.
Model
RESOLUTION
ANALOG INPUTS
Voltage Ranges
Bipolar
Unipolar
Impedance (Direct Input)
0 V to +5 V, ±2.5 V
0 V to +10 V, ±5.0 V
0 V to +20 V, ±10 V
DIGITAL INPUTS1
Convert Command
Logic Loading
TRANSFER CHARACTERISTICS2
(ACCURACY)
Gain Error
Offset Error
Unipolar
Bipolar
Linearity Error (Max)
Inherent Quantization Error
Differential Linearity Error
POWER SUPPLY SENSITIVITY
±15 V DC (±0.75 V)
+5 V DC (±0.25 V)
CONVERSION TIME5
12 Bits (AD1376)
14 Bits (AD1376)
16 Bits (AD1376)
14 Bits (AD1377)
16 Bits (AD1377)
POWER SUPPLY REQUIREMENTS
Analog Supplies
Digital Supply
AD1376 Power Consumption
+15 V Supply Drain
−15 V Supply Drain
+5 V Supply Drain
AD1377 Power Consumption
+15 V Supply Drain
−15 V Supply Drain
+5 V Supply Drain
WARM-UP TIME
AD1376JD/AD1377JD
Min Typ
Max
16
AD1376KD/AD1377KD
Min Typ
Max
16
±2.5
±5
±10
0 to 5
0 to 10
0 to 20
±2.5
±5
±10
0 to 5
0 to 10
0 to 20
1.88 1.88
3.75 3.75
7.50 7.50
Trailing edge of positive 50 ns (min) pulse
11
±0.053
±0.053
±0.053
±0.006
±1/2
±0.003
0.0015
0.001
11.5
13.5
15.5
+14.5
−14.5
+4.75
+15
−15
+5
600
+10
−23
+18
600
+10
−23
+18
1
±0.2 ± 0.053
±0.1 ±0.053
±0.2 ±0.053
±0.003
±1/2
±0.003
0.0015
0.001
13 11.5
15 13.5
17 15.5
8.75
10
+15.5
−15.5
+5.25
800
800
+14.5
−14.5
+4.75
+15
−15
+5
600
+10
−23
+18
600
+10
−23
+18
1
± 0.2
±0.1
±0.2
13
15
17
8.75
10
+15.5
−15.5
+5.25
800
800
Unit
Bits
V
V
V
V
V
V
V
kΩ
kΩ
kΩ
LS TTL Load
%
% of FSR4
% of FSR
% of FSR
LSB
% of FSR
% of FSR/% ∆VS
% of FSR/% ∆VS
µs
µs
µs
µs
µs
V dc
V dc
V dc
mW
mA
mA
mA
mW
mA
mA
mA
Minutes
Rev. D | Page 3 of 12



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AD1376/AD1377
AD1376JD/AD1377JD
AD1376KD/AD1377KD
Model
Min Typ
Max Min Typ
Max
DRIFT6
Gain
±15 ±5
±15
Offset
Unipolar
±2 ±4 ±2 ±4
Bipolar
±10 ±3
±10
Linearity
±2
±3 ±0.3
±2
Guaranteed No Missing Code
Temperature Range
0 to 70 (13 Bits)
0 to 70 (14 Bits)
DIGITAL OUTPUT1
(All Codes Complementary)
Parallel Output Codes7
Unipolar
Bipolar
CSB
COB, CTC8
CSB
COB, CTC8
Output Drive
5
5
Status
Status Output Drive
Internal Clock9
Logic 1 During
Conversion
5
Logic 1 During
Conversion
5
Clock Output Drive
55
Frequency
1040/1750
1040/1750
TEMPERATURE RANGE
Specification
0 to 70
0 to 70
Operating
−25 to +85
−25 to +85
Storage
−55 to +125
−55 to +125
1 Logic 0 = 0.8 V max; Logic 1 = 2.0 V min for inputs. For digital outputs, Logic 0 = 0.4 V max. Logic 1 = 2.4 V min.
2 Tested on ±10 V and 0 V to +10 V ranges.
3 Adjustable to zero.
4 Full-scale range.
5 Conversion time may be shortened with “short cycle” set for lower resolution.
6 Guaranteed but not 100% production tested.
7 CSB–Complementary Straight Binary. COB–Complementary Offset Binary. CTC–Complementary Twos Complement.
8 CTC coding obtained by inverting MSB (Pin 1).
9 With Pin 23, clock rate controls tied to digital ground.
Unit
ppm/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
°C
LSTTL Loads
LSTTL Loads
LSTTL Loads
kHz
°C
°C
°C
Rev. D | Page 4 of 12



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