ABB0203 Datasheet PDF - Abracon Corporation

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ABB0203
Abracon Corporation

Part Number ABB0203
Description Low Skew Output Buffer
Page 6 Pages


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ABB0203
Low Skew Outpwwuwt.DBatuaSfhfeeet4rU.com
FEATURES
Frequency range 75 ~ 180MHz.
Internal phase locked loop will allow spread spec-
trum modulation on reference clock to pass to the
outputs (up to 100kHz SST modulation).
Zero input - output delay.
Less than 700 ps device - device skew.
Less than 250 ps skew between outputs.
Less than 150 ps cycle - cycle jitter.
Output Enable function tri-state outputs.
3.3V operation.
Available in 8-Pin 150mil SOIC.
DESCRIPTION
The ABB0203 is a high performance, low skew, low
jitter zero delay buffer designed to distribute high
speed clocks and is available in an 8-pin SOIC pack-
age. It has four outputs that are synchronized with the
input. The synchronization is established via CLKOUT
feed back to the input of the PLL. Since the skew be-
tween the input and output is less than ±350 ps, the
device acts as a zero delay buffer.
PIN CONFIGURATION
REF
CLK2
CLK1
GND
1
2
3
4
8 CLKOUT
7 CLK4
6 VDD
5 CLK3
Remark
If REF clock is stopped for more than 10us after it has already been
provided to the chip, and after power-up, the output clocks will
disappear. In that instance, a full power-up reset is required in order
to reactivate the output clocks.
BLOCK DIAGRAM
REF
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 1



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ABB0203
Low Skew Outwpwuw.tDaBtaSuhfeefte4Ur.com
PIN DESCRIPTIONS
Name
Number Type
Description
REF1
CLK22
CLK12
GND
CLK32
VDD
CLK42
CLKOUT2
1
I
Input reference frequency. Spread spectrum modulation on this signal will be
passed to the output (up to 100kHz SST modulation).
2 O Buffered clock output.
3 O Buffered clock output.
4 P Ground.
5 O Buffered clock output.
6 P 3.3V Power Supply.
7 O Buffered clock output.
8 O Buffered clock output. Internal feed back on this pin.
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
VDD 4.6 V
VI
-0.5 VDD+0.5
V
VO
-0.5 VDD+0.5
V
TS -65 150 °C
TA -40 85 °C
TJ 125 °C
260 °C
2 kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Electrical Characteristics
PARAMETERS
Supply Voltage
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Power Down Supply Current
Supply Current
SYMBOL
VDD
VIL
VIH
IIL
IIH
VOL
VOH
IDD
IDD
CONDITIONS
VIN = 0V
VIN = VDD
IOL = 50mA
IOH = 50mA
REF = 0MHz
Unloaded outputs at 133MHz,
SEL inputs at VDD or GND
MIN.
2.97
2.0
2.4
TYP.
19
0.10
0.25
2.9
0.3
35
MAX.
3.63
0.8
50.0
100.0
0.4
50.0
45
UNITS
V
V
V
µA
µA
V
V
µA
mA
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 2



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3. Switching Characteristics
PARAMETERS
Output Frequency
Duty Cycle ( t2 ÷ t1 )
Duty Cycle ( t2 ÷ t1 )
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
Device to Device Skew
Cycle to Cycle Jitter
PLL Lock Time
Jitter; Absolute Jitter
Jitter; 1-sigma
SYMBOL
t1
Dt1
Dt2
Tr
Tf
Tskew
Tdelay
Tdsk-dsk
Tcyc-cyc
Tlock
Tjabs
Tj1-s
DESCRIPTION
Measured at 1.4V, CL=30pF
Measured at 1.4V
Measured between 0.8V
and 2.0V, CL=30pF
Measured between 2.0V
and 0.8V, CL=30pF
All outputs equally loaded,
CL=20pF
Measured at 1.4V
Measured at VDD/2 on the
CLKOUT pins of devices
Measured at 133MHz,
loaded outputs
Stable power supply, valid
clock presented on REF pin
At 10,000 cycles, CL=30pF
At 10,000 cycles, CL=30pF
ABB0203
Low Skew Outwpwuw.tDaBtaSuhfeefte4Ur.com
MIN.
75
40.0
45.0
TYP.
50.0
50.0
1.2
1.2
0
0
70
10
MAX.
180
60.0
55.0
1.5
1.5
250
±350
700
150
1.0
100
20
UNITS
MHz
%
%
ns
ns
ps
ps
ps
ps
ms
ps
ps
SWITCHING WAVEFORMS
Duty Cycle Timing
t1
t2
1.4V
1.4V
1.4V
Output - Output Skew
Output
1.4V
Output
1.4V
TSKEW
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 3



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SWITCHING WAVE FORMS
All Outputs Rise/Fall Time
Output
2.0V
0.8V
tr
2.0V
0.8V
tf
Input to Output Propagation Delay
VDD/2
Input
Output
VDD/2
Tdelay
ABB0203
Low Skew Outwpwuw.tDaBtaSuhfeefte4Ur.com
3.3V
0V
Device to Device Skew
VDD/2
Device1 CLKOUT
Device2 CLKOUT
VDD/2
Tdsk - dsk
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 4



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