A6259 Datasheet PDF - Allegro

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A6259
Allegro

Part Number A6259
Description 8-Bit Addressable DMOS Power Driver
Page 11 Pages


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A6259
8-Bit Addressable DMOS Power Driver
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: April 30, 2007
Recommended Substitutions:
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.



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6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
POWER
GROUND
1
LOGIC
SUPPLY
2
VDD
S 0 (LSB) 3
OUT 0 4
OUT1 5
OUT 2 6
OUT 3 7
S1 8
LOGIC 9
GROUND
POWER 10
GROUND
20
POWER
GROUND
19 CLEAR
18 DATA
17 OUT7
16 OUT6
15 OUT5
14 OUT 4
EN 13 ENABLE
12 S2 (MSB)
11 POWER
GROUND
Dwg. PP-050-2
Note that the A6259KA (DIP) and the A6259KLW
(SOIC) are electrically identical and share a
common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ............................ 50 V
Output Drain Current,
Continuous, IO ...................... 250 mA*
Peak, IOM ............................. 750 mA*†
Peak, IOM ................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS ............................................. 75 mJ
Logic Supply Voltage, VDD .............. 7.0 V
Input Voltage Range,
VI ............................... -0.3 V to +7.0 V
Package Power Dissipation,
PD ....................................... See Graph
Operating Temperature Range,
TA ............................. -40°C to +125°C
Storage Temperature Range,
TS ............................. -55°C to +150°C
*Each output, all outputs on.
† Pulse duration 100 µs, duty cycle 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to
damage if exposed to extremely high static
electrical charges.
The A6259KA and A6259KLW combine a 3-to-8 line CMOS
decoder and accompanying data latches, control circuitry, and DMOS
outputs in a multi-functional power driver capable of storing single-line
data in the addressable latches or use as a decoder or demuliplexer.
Driver applications include relays, solenoids, and other medium-current
or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with micro-
processor-based systems. Use with TTL may require appropriate pull-
up resistors to ensure an input logic high. Four modes of operation are
selectable with the CLEAR and ENABLE inputs.
The addressed DMOS output inverts the DATA input with all
unaddressed outputs remaining in their previous states. All of the output
drivers are disabled (the DMOS sink drivers turned off) with the
CLEAR input low and the ENABLE input high. The A6259KA/KLW
DMOS open-drain outputs are capable of sinking up to 750 mA. Similar
devices with reduced rDS(on) are available as the A6A259.
The A6259KA is furnished in a 20-pin dual in-line plastic package.
The A6259KLW is furnished in a 20-lead wide-body, small-outline
plastic package (SOIC) with gull-wing leads for surface-mount applica-
tions. Copper lead frames, reduced supply current requirements, and
low on-state resistance allow both devices to sink 150 mA from all
outputs continuously, to ambient temperatures over 85°C.
FEATURES
s 50 V Minimum Output Clamp Voltage
s 250 mA Output Current (all outputs simultaneously)
s 1.3 Typical rDS(on)
s Low Power Consumption
s Replacements for TPIC6259N and TPIC6259DW
Always order by complete part number:
Part Number
A6259KA
A6259KLW
Package
20-pin DIP
20-lead SOIC
RθJA
55°C/W
70°C/W
RθJC
25°C/W
17°C/W



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6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
2.5
2.0
SUFFIX 'A', R
1.5 SUFFIX 'LW', R θJA = 55°C/W
1.0 θJA = 70°C/W
0.5
0
25
50 75 100 125
AMBIENT TEMPERATURE IN °C
150
Dwg. GS-004A
VDD
IN
LOGIC SYMBOL
30
8 8M 0/7
12 2
13 G8
18 Z9
19 Z10
9,0D
10,0R
9,1D
10,1R
9,2D
10,2R
9,3D
10,3R
9,4D
10,4R
9,5D
10,5R
9,6D
10,6R
9,7D
10,7R
4
5
6
7
14
15
16
17
Dwg. FP-046
OUT
Dwg. EP-010-15
LOGIC INPUTS
Dwg. EP-063
DMOS POWER DRIVER OUTPUT
FUNCTION TABLE
Inputs
CLEAR ENABLE DATA
H LH
H LL
H HX
L LH
L LL
L HX
Addressed
OUTPUT
L
H
R
L
H
H
Other
OUTPUTs
R
R
R
H
H
H
Function
Addressable
Latch
Memory
8-Line
Demultiplexer
Clear
L = Low Logic Level H = High Logic Level X = Irrelevant R = Previous State
LATCH SELECTION TABLE
Select Inputs
Addressed
S2 (MSB) S1 S0 (LSB) OUTPUT
LLL
0
L LH
1
LHL
2
L HH
3
HL L
4
HLH
5
HH L
6
HHH
7
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.



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6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
FUNCTIONAL BLOCK DIAGRAM
S0
(LSB)
S1
S2
(MSB)
LOGIC
SUPPLY
LOGIC
GROUND
V DD
DATA
ENABLE
(ACTIVE LOW)
CLEAR
(ACTIVE LOW)
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point.
OUT 0
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
POWER
GROUND
Dwg. FP-047-1
www.allegromicro.com



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