A3R56E40ABF Datasheet PDF - Zentel

www.Datasheet-PDF.com

A3R56E40ABF
Zentel

Part Number A3R56E40ABF
Description 256Mb DDRII Synchronous DRAM
Page 30 Pages


A3R56E40ABF datasheet pdf
View PDF for PC
A3R56E40ABF pdf
View PDF for Mobile


No Preview Available !

A3R56E40ABF
256Mb DDRII Synchronous DRAM
256Mb DDRII SDRAM Specification
A3R56E40ABF
Zentel Electronics Corp.
Revision 1.2
Dec., 2012



No Preview Available !

A3R56E40ABF
256Mb DDRII Synchronous DRAM
Specifications
Density: 256M bits
Organization
4M words × 16 bits × 4 banks (A3R56E40ABF)
Package
84-ball FBGA(μBGA) (A3R56E40ABF)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Data rate: 1066Mbps/800Mbps(max.)
1KB page size (A3R56E40ABF)
Row address: A0 to A12
Column address: A0 to A8
Four internal banks for concurrent operation
Interface: SSTL_18
Burst lengths (BL): 4, 8
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
/CAS Latency (CL): 3, 4, 5, 6, 7
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8μs at 0°C TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
Double-data-rate architecture; two data transfers per clock
cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS) is
transmitted/received with data for capturing data at the
receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die-Termination for better signal quality
/DQS can be disabled for single-ended
Data Strobe operation
Off-Chip Driver (OCD) impedance adjustment is not
supported
Zentel Electronics Corporation reserve the right to change products or specification without notice.
Revision 1.2
Page 1 / 71
Dec., 2012



No Preview Available !

Ordering Information
Organization
Part number
(words × bits)
A3R56E40ABF-AH
A3R56E40ABF-8E
16M × 16
Internal
Banks
4
Part Number
A3R56E40ABF
256Mb DDRII Synchronous DRAM
Speed bin
(CL-tRCD-tRP)
DDR2-1066 (7-7-7)
DDR2-800 (5-5-5)
Package
84-ball FBGA
A 3 R 56 E 4 0A BF - 8E
Speed
AH: DDR2-1066(7-7-7)
8E: DDR2-800(5-5-5)
Package Type
Die version
BF: FBGA
0A: Version 0A
I/O Configuration 4: x16
Classification
E: DDR2
Density
56: 256 Mbits
Interface
R: SSTL_18
Product Line
3: DRAM
Zentel Memory
Revision 1.2
Page 2 / 71
Dec., 2012



No Preview Available !

Pin Configurations
/xxx indicates active low signal.
A3R56E40ABF
256Mb DDRII Synchronous DRAM
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ15
UDQS, /UDQS
LDQS, /LDQS
/CS
/RAS,/CAS,/WE
CKE
CK,/CK
UDM, LDM
Function
Address inputs
Bank select
Data input/output
Differential data strobe
Chip select
Command input
Clock enable
Differential clock input
Write data mask
Notes: 1.Not internally connected with die.
2.Don’t use other than reserved functions.
Pin name
ODT
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
NC*1
NU*2
Function
ODT control
Power Supply
Ground
Power Supply for DQ circuit
Ground for DQ circuit
Input reference voltage
Power Supply for DLL circuit
Ground for DLL circuit
No connection
Not usable
Revision 1.2
Page 3 / 71
Dec., 2012



A3R56E40ABF datasheet pdf
Download PDF
A3R56E40ABF pdf
View PDF for Mobile


Related : Start with A3R56E40AB Part Numbers by
A3R56E40ABF 256Mb DDRII Synchronous DRAM A3R56E40ABF
Zentel
A3R56E40ABF pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Privacy Policy + Contact