A3R1GE40JBF Datasheet PDF - Zentel

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A3R1GE40JBF
Zentel

Part Number A3R1GE40JBF
Description 1Gb DDRII Synchronous DRAM
Page 30 Pages


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A3R1GE30JBF
A3R1GE40JBF
1Gb DDRII Synchronous DRAM
1Gb DDRII SDRAM Specification
A3R1GE30JBF
A3R1GE40JBF
Zentel Electronics Corp.
Revision 1.0
Dec., 2014



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A3R1GE30JBF
A3R1GE40JBF
1Gb DDRII Synchronous DRAM
Specifications
Features
Density: 1G bits
Organization
16M words × 8 bits × 8 banks (A3R1GE30JBF)
8M words × 16 bits × 8 banks (A3R1GE40JBF)
Package
60-ball FBGA(μBGA) (A3R1GE30JBF)
84-ball FBGA(μBGA) (A3R1GE40JBF)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Data rate: 1066Mbps/800Mbps (max.)
1KB page size (A3R1GE30JBF)
Row address: A0 to A13
Column address: A0 to A9
2KB page size (A3R1GE40JBF)
Row address: A0 to A12
Column address: A0 to A9
Eight internal banks for concurrent operation
Interface: SSTL_18
Burst lengths (BL): 4, 8
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
/CAS Latency (CL): 3, 4, 5, 6, 7
Recharge: auto recharge option for each burst access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8μs at TC+85°C
3.9μs at TC+85°C
Industrial grade compliant with AEC-Q100 grade3
Automotive grade compliant with AEC-Q100 grade2
Operating case temperature range
TC = 0°C to +95°C (Commercial grade)*
TC = -40°C to +95°C (Industrial grade)*
TC = -40°C to +105°C (Automotive grade)*
Double-data-rate architecture; two data transfers per clock
cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS) is
transmitted/received with data for capturing data at the
receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die-Termination for better signal quality
Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
Off-Chip Driver (OCD) impedance adjustment is not
supported
Note: Refer to operating temperature condition on page 5 for
details
Zentel Electronics Corporation reserve the right to change products or specification without notice.
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A3R1GE30JBF
A3R1GE40JBF
1Gb DDRII Synchronous DRAM
Ordering Information
Part number
A3R1GE30JBF-AH
A3R1GE30JBF-AHI
A3R1GE30JBF-AHA
A3R1GE30JBF-8E
A3R1GE30JBF-8EI
A3R1GE30JBF-8EA
A3R1GE40JBF-AH
A3R1GE40JBF-AHI
A3R1GE40JBF-AHA
A3R1GE40JBF-8E
A3R1GE40JBF-8EI
A3R1GE40JBF-8EA
Organization
(words × bits)
128M × 8
64M × 16
Internal
Banks
8
8
Speed bin
(CL-tRCD-tRP)
DDR2-1066 (7-7-7)
DDR2-1066 (7-7-7)
DDR2-1066 (7-7-7)
DDR2- 800 (5-5-5)
DDR2- 800 (5-5-5)
DDR2- 800 (5-5-5)
DDR2-1066 (7-7-7)
DDR2-1066 (7-7-7)
DDR2-1066 (7-7-7)
DDR2- 800 (5-5-5)
DDR2- 800 (5-5-5)
DDR2- 800 (5-5-5)
Package
60-ball FBGA
84-ball FBGA
Grade
Commercial
Industrial
Automotive
Commercial
Industrial
Automotive
Commercial
Industrial
Automotive
Commercial
Industrial
Automotive
Part Number
A 3 R 1G E 4 0J BF - 8E I
Operating
Temperature
Speed
Package Type
Blank: Commercial (0 ~ 95)
I: Industrial (-40 ~ 95)
A: Automotive (-40 ~ 105)
8E: DDR2-800
AH: DDR2-1066
BF: FBGA
Die version
IO Configuration
Classification
0J: Version 0J
3: x8
4: x16
E: DDR2
Density
1G: 1Gbits
Interface
R: SSTL-18
Product line
3: DRAM
Zentel memory
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Pin Configurations
/xxx indicates active low signal.
A3R1GE30JBF
A3R1GE40JBF
1Gb DDRII Synchronous DRAM
Pin name
A0 to A13
BA0, BA1,BA2
DQ0 to DQ15
DQS,/DQS
UDQS, /UDQS
LDQS, /LDQS
RDQS,/RDQS
/CS
/RAS,/CAS,/WE
CKE
CK,/CK
DM
UDM, LDM
Function
Address inputs
Bank select
Data input/output
Differential data strobe
Differential data strobe for read
Chip select
Command input
Clock enable
Differential clock input
Write data mask
Notes: 1. Not internally connected with die.
2. Don’t use other than reserved functions.
Pin name
ODT
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
NC*1
NU*2
Function
ODT control
Power Supply
Ground
Power Supply for DQ circuit
Ground for DQ circuit
Input reference voltage
Power Supply for DLL circuit
Ground for DLL circuit
No connection
Not usable
Revision 1.0
Page 3 / 72
Dec., 2014



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