A3930 Datasheet PDF - Allegro MicroSystems

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A3930
Allegro MicroSystems

Part Number A3930
Description (A3930 / A3931) Automotive 3-Phase BLDC Controller and MOSFET Driver
Page 21 Pages


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A3930 and A3931
Automotive 3-Phase BLDC Controller and MOSFET Driver
Features and Benefits
High current 3-phase gate drive for N-channel MOSFETs
Synchronous rectification
Cross-conduction protection
Charge pump and top-off charge pump for 100% PWM
Integrated commutation decoder logic
Operation over 5.5 to 50 V supply voltage range
Extensive diagnostics output
Provides +5 V Hall sensor power
Low-current sleep mode
Package: 48 Lead LQFP with exposed
thermal pad (suffix JP)
Description
TheA3930 andA3931 are 3-phase brushless dc (BLDC) motor
controllers for use with N-channel external power MOSFETs.
They incorporate much of the circuitry required to design a
cost effective three-phase motor drive system, and have been
specifically designed for automotive applications.
A key automotive requirement is functionality over a wide
input supply range. A unique charge pump regulator provides
adequate (>10V) gate drive for battery voltages down to 7V,
and allows the device to operate with a reduced gate drive at
battery voltages down to 5.5V. Power dissipation in the charge
pump is minimized by switching from a voltage doubling mode
at low supply voltage to a dropout mode at the nominal running
voltage of 14V.
A bootstrap capacitor is used to provide the above-battery
supply voltage required for N-channel MOSFETs. An internal
charge pump for the high-side drive allows for dc (100% duty
cycle) operation.
Internal fixed-frequency PWM current control circuitry can
be used to regulate the maximum load current. The peak
load current limit is set by the selection of an input reference
voltage and external sensing resistor. The PWM frequency is
set by a user-selected external RC timing network. For added
flexibility, the PWM input can be used to provide speed and
Continued on the next page…
Typical Application
3930-DS
Preliminary Data Sheet Subject to Change Without Notice April 6, 2006



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A3930 and
A3931
Automotive 3-Phase BLDC Controller
and MOSFET Driver
Description (continued)
torque control, allowing the internal current control circuit to set
the maximum current limit.
Efficiency is enhanced by using synchronous rectification. The
power FETs are protected from shoot-through by integrated
crossover control with dead time. The dead time can be set by a
single external resistor.
The A3930 and A3931 only differ in their response to the all-zero
combination on the Hall inputs. In this state, the A3930 indicates
a logic fault, but the A3931 prepositions the motor in an unstable
starting position suitable for start-up algorithms in microprocessor-
driven “sensor-less” control systems.
Both devices are supplied in a 48-pin LQFP with exposed thermal
pad. This is a small footprint (81 mm2) power package, that is lead
(Pb) free, with 100% matte tin leadframe plating.
Selection Guide
Part Number
A3930KJP-T
A3931KJP-T
Option
Hall short detection
Prepositioning
Packing
250 pieces/tray
Terminals
48
Package
LQFP surface mount
Absolute Maximum Ratings
Parameter
Load Supply Voltage
Logic Input/Output Voltage
Output Voltage Range
Operating Temperature Range (K)
Junction Temperature
Storage Temperature Range
Symbol
VBB
VRESET
VGHx
VGLx
VCx
VSx
TA
TJ
TS
Conditions
VBB pin
RESET pin input
Remaining logic pins
GHA, GHB, and GHC pins
GLA, GLB, and GLC pins
CA, CB, and CC pins
SA, SB, and SC pins
CSP, CSN, and LSS pins
CSO, VDSTH pins
VDRAIN pin
Min.
–0.3
–0.3
–0.3
VSx
–5
–5
–4
–0.3
–40
–55
Typ.
Max.
50
6
7
VSx+ 15
16
VSx+ 15
45
6.5
6.5
55
135
150
150
Units
V
V
V
V
V
V
V
V
V
°C
°C
°C
Preliminary Data Sheet
Subject to Change Without Notice
April 6, 2006
Allegro MicroSystems, Inc.
2
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com



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A3930 and
A3931
Automotive 3-Phase BLDC Controller
and MOSFET Driver
Functional Block Diagram
VBAT+
QV5
V5BD
V5
CV5
MODE
COAST
BRAKE
RESET
DIR
H1
VBB
+5V Ref
Control
Logic
CP2
CP
CP1
Charge
Pump
Regulator
Phase A of three phases
Charge
Pump
Boostrap
Monitor
High-Side
Drive
VREG
CREG
VDRAIN
P
CA
CBOOTA
GHA
RGHA
SA
H1
H2
H3
&B
V5
&C
H2
H3
RDEAD
PWM
TACHO
DIRO
ESF
FF1
FF2
Pad
VREG
Low-Side
Drive
GLA
RGLA
LSS
&A
Diagnostics and
Protection
–UVLO
–TSD
–Short to Supply
–Short to Ground
–Shorted Winding
–Low Load
R
Q
S
OSC
Blanking
VDSTH
RC
RT
REF CSOUT AGND
CT
TEST
CSP
CSN
RSENSE
P
Preliminary Data Sheet
Subject to Change Without Notice
April 6, 2006
Allegro MicroSystems, Inc.
3
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com



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A3930 and
A3931
Automotive 3-Phase BLDC Controller
and MOSFET Driver
ELECTRICAL CHARACTERISTICS at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1
Characteristics
Symbol
Test Conditions
Min.
Supply and Reference
VBB Functional Operating Range6
VBB
Function correct, parameters not
guaranteed
5.5
VBB Quiescent Current
V5 Quiescent Current
VREG Output Voltage
Bootstrap Diode Forward Voltage
Bootstrap Diode Resistance
Bootstrap Diode Current Limit
Top-off Charge Pump Current Limit
Cx Top-off Charge Pump Source Current
V5 Output Voltage
VBE of External Transistor QV5
V5BD Base Drive Capability for QV52
IBBQ
IBBS
IV5Q
VREG
VfBOOT
rD
IDBOOT
ITOCPM
ICx
V5
VBEEXT
I5BD
RESET = High, outputs = Low
RESET = Low, sleep mode
RESET = High, outputs = Low
VBB > 7.5 V, IREG = 0 to 15 mA
6 V < VBB < 7.5 V
IREG = 0 to 15 mA
5.5 V < VBB < 6 V, IREG < 10 mA
ID = 10 mA
ID = 100 mA
rD(100 mA) = (VfBOOT(150 mA)
VfBOOT(50 mA)) / 100 mA
VCx-VSx= 8 V, VBB= 14 V, GHx = High
12.5
2 × VBB
–2.5
9
0.4
1.5
6
250
40
4.75
Gate Output Drive
Turn-On Rise Time
Turn-Off Fall Time
Pull-Up On Resistance
Pull-Down On Resistance
Short-Circuit Current – Source2
Short-Circuit Current – Sink
GHx Output Voltage
tr
tf
RDS(on)UP
RDS(on)DN
ISC(source)
ISC(sink)
VGHx
CLOAD = 3300 pF, 20% to 80% points
CLOAD = 3300 pF, 80% to 20% points
TJ = 25°C, IGHx= –150 mA
TJ = 150°C, IGHx= –150 mA
TJ = 25°C, IGLx= 150 mA
TJ = 150°C, IGLx= 150 mA
TJ = 25°C
TJ = 25°C
tw < 10 μs
Bootstrap capacitor fully charged
3
5
1
1.5
VCx – 0.2
GLx Output Voltage
VGLx
VREG
0.2
Turn-Off Propagation Delay
tp(off)
From input change to unloaded gate
output change
Dead Time (turn-off to turn-on delay)
tDEAD
RDEAD = 5 kΩ
RDEAD = 50 kΩ
RDEAD = 400 kΩ
RDEAD = tied to V5
815
Typ.
11
13
10
0.7
2.2
10
500
200
5
60
40
4
6
1.5
2.3
–500
850
90
180
960
3.3
6
Max. Units
50
14
10
5
13.75
1.0
2.8
20
750
5.25
1
–2
V
mA
μA
mA
V
V
V
V
V
Ω
mA
μA
μA
V
V
mA
– ns
– ns
5Ω
7Ω
2Ω
3Ω
– mA
– mA
–V
–V
150
1110
ns
ns
ns
μs
μs
Continued on the next page...
Preliminary Data Sheet
Subject to Change Without Notice
April 6, 2006
Allegro MicroSystems, Inc.
4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com



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