A29L040A Datasheet PDF - AMIC Technology

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A29L040A
AMIC Technology

Part Number A29L040A
Description 512K X 8 Bit CMOS 3.0 Volt-only Uniform Sector Flash Memory
Page 30 Pages


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A29L040A Series
Preliminary
512K X 8 Bit CMOS 3.0 Volt-only,
Uniform Sector Flash Memory
Document Title
512K X 8 Bit CMOS 3.0 Volt-only, Uniform Sector Flash Memory
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
March 9, 2005
Remark
Preliminary
PRELIMINARY (March, 2005, Version 0.0)
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A29L040A Series
Preliminary
512K X 8 Bit CMOS 3.0 Volt-only,
Uniform Sector Flash Memory
Features
Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
- Regulated voltage range: 3.0 to 3.6 volt read and write
operations for compatibility with high performance 3.3
volt microprocessors
Access times:
- 70 (max.)
Current:
- 4 mA typical active read current
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
Flexible sector architecture
- 8 uniform sectors of 64 Kbyte each
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within that
sector
Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors
and verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies bytes at specified addresses
Typical 100,000 program/erase cycles per sector
20-year data retention at 125°C
- Reliable operation for the life of the system
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
- Superior inadvertent write protection
Data Polling and toggle bits
- Provides a software method of detecting completion of
program or erase operations
Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
Package options
- 32-pin DIP, PLCC, TSOP (8mm x 20mm), sTSOP
(8mm x 13.4mm), sTSOP (8mm x 14mm).
General Description
The A29L040A is a 3.0 volt-only Flash memory organized as
524,288 bytes of 8 bits each. The 512 Kbytes of data are
further divided into eight sectors of 64 Kbytes each for
flexible sector erase capability. The 8 bits of data appear on
I/O0 - I/O7 while the addresses are input on A0 to A18. The
A29L040A is offered in 32-pin PLCC, TSOP (8mm x 20mm)
or sTSOP (8mm x 13.4mm) packages. This device is
designed to be programmed in-system with the standard
system 3.0 volt VCC supply. Additional 12.0 volt VPP is not
required for in-system write or erase operations. However,
the A29L040A can also be programmed in standard EPROM
programmers.
The A29L040A has a second toggle bit, I/O2, to indicate
whether the addressed sector is being selected for erase,
and also offers the ability to program in the Erase Suspend
mode. The standard A29L040A offers access times of 70ns,
allowing high-speed microprocessors to operate without wait
states. To eliminate bus contention the device has separate
chip enable ( CE ), write enable ( WE ) and output enable
( OE ) controls.
The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29L040A is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.
The host system can detect whether a program or erase
operation is complete by reading the I/O7 ( Data Polling) and
I/O6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
PRELIMINARY (March, 2005, Version 0.0)
1
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Aw2w9w.LDa0t4aS0heAet4SU.ecormies
contents of other sectors. The A29L040A is fully erased
when shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the sectors
of memory. This can be achieved via programming
equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program
data to, any other sector that is not selected for erasure.
True background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
Pin Configurations
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PLCC
A7 5
29 A14
A6 6
28 A13
A5 7
27 A8
A4 8
A3 9
26 A9
A29L040AL 25 A11
A2 10
24 OE
A1 11
23 A10
A0 12
22 CE
I/O0 13
21 I/O7
32-pin TSOP (8mm X 20mm)
32-pin sTSOP (8mm X 13.4mm)
32-pin sTSOP (8mm X 14mm)
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A29L040AV (8mm x 20mm)
A29L040AX (8mm x 13.4mm)
A29L040AY (8mm x 14mm)
32 OE
31 A10
30 CE
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 VSS
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
PRELIMINARY (March, 2005, Version 0.0)
2
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Block Diagram
VCC
VSS
WE State
Control
Command
Register
CE
OE
A0-A18
VCC Detector
Erase Voltage
Generator
Aw2w9w.LDa0t4aS0heAet4SU.ecormies
I/O0 - I/O7
Input/Output
Buffers
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB Data Latch
Timer
STB
Y-Decoder
X-decoder
Y-Gating
Cell Matrix
Pin Descriptions
Pin No.
A0 - A18
I/O0 - I/O7
CE
WE
OE
VSS
VCC
Description
Address Inputs
Data Inputs/Outputs
Chip Enable
Write Enable
Output Enable
Ground
Power Supply
PRELIMINARY (March, 2005, Version 0.0)
3
AMIC Technology, Corp.



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