A29DL32X Datasheet PDF - AMIC Technology

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A29DL32X
AMIC Technology

Part Number A29DL32X
Description 32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only a Simultaneous Operation Flash Memory
Page 30 Pages


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Preliminary
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A29DL32x Series
32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memory
Document Title
4M X 8 Bit / 2M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
May 25, 2005
Remark
Preliminary
PRELIMINARY (May, 2005, Version 0.0)
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A29DL32x Series
Preliminary
32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
- Data can be continuously read from one bank while
executing erase/program functions in other bank
- Zero latency between read and write operations
Multiple bank architectures
- Three devices available with different bank sizes (refer to
Table 2)
Package options
- 48-ball TFBGA
- 48-pin TSOP
Top or bottom boot block
Manufactured on 0.18 µm process technology
- Compatible with AMD AM29DL32xD device
Compatible with JEDEC standards
- Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
High performance
- Access time as fast as 70ns
- Program time: 7µs/word typical utilizing Accelerate
function
Ultra low power consumption (typical values)
- 2mA active read current at 1MHz
- 10mA active read current at 5MHz
- 200nA in standby or automatic sleep mode
Minimum 1 million write cycles guaranteed per sector
20 Year data retention at 125°C
- Reliable operation for the life of the system
SOFTWARE FEATURES
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
- Suspends erase operations to allow programming in
same bank
Software temporary sector/sector block unprotect command
Software sector protect/unprotect command
Data Polling and Toggle Bits
- Provides a software method of detecting the status of
program or erase cycles
Unlock Bypass Program command
- Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
Any combination of sectors can be erased
Ready/ Busy output (RY/BY )
- Hardware method for detecting program or erase cycle
completion
Hardware reset pin (RESET )
- Hardware method of resetting the internal state machine
to reading array data
WP /ACC input pin
- Write protect ( WP ) function allows protection of two
outermost boot sectors, regardless of sector protect
status
- Acceleration (ACC) function accelerates program timing
Sector protection
- Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program
or erase operation within that sector
- Temporary Sector Unprotect allows changing data in
protected sectors in-system
PRELIMINARY (May, 2005, Version 0.0)
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A29DL32x Series
GENERAL DESCRIPTION
The A29DL32x family consists of 32 megabit, 3.0 volt-only
flash memory devices, organized as 2,097,152 words of 16
bits each or 4,194,304 bytes of 8 bits each. Word mode data
appears on I/O0–I/O15; byte mode data appears on I/O0–I/O7.
The device is designed to be programmed in-system with the
standard 3.0 volt VCC supply, and can also be programmed
in standard EPROM programmers.
The device is available with an access time of 70, 80, 90, or
120 ns. The devices are offered in 48-pin TSOP and 48-ball
Fine-pitch TFBGA. Standard control pins—chip enable ( CE ),
write enable ( WE ), and output enable ( OE )—control
normal read and write operations, and avoid bus contention
issues.
The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
Simultaneous Read/Write Operations with Zero
Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory space into
two banks. The device can improve overall system
performance by allowing a host system to program or erase
in one bank, then immediately and simultaneously read from
the other bank, with zero latency. This releases the system
from waiting for the completion of program or erase
operations.
The A29DL32x devices use multiple bank architectures to
provide flexibility for different applications. Three devices are
available with these bank sizes:
Device
DL322
Bank 1
4 Mb
Bank 2
28 Mb
DL323
8 Mb
24 Mb
DL324
16 Mb
16 Mb
A29DL32x Features
The device offers complete compatibility with the JEDEC
single-power-supply Flash command set standard.
Commands are written to the command register using
standard microprocessor write timings. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
The host system can detect whether a program or erase
operation is complete by using the device status bits:
RY/ BY pin, I/O7 ( Data Polling) and I/O6/I/O2 (toggle bits).
After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any
combination of the sectors of memory. This can be achieved
in-s y s t e m or via programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system
can also place the device into the standby mode. Power
consumption is greatly reduced in both modes.
PRELIMINARY (May, 2005, Version 0.0)
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Pin Configurations
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
NC
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TSOP (I)
A29DL32xV
Aw2w9w.DDaLta3Sh2exet4SU.ecormies
48 A16
47 BYTE
46 VSS
45 I/O15(A-1)
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 I/O12
38 I/O 4
37 VCC
36 I/O11
35 I/O3
34 I/O10
33 I/O 2
32 I/O 9
31 I/O 1
30 I/O 8
29 I/O 0
28 OE
27 VSS
26 CE
25 A0
TFBGA
TFBGA
Top View, Balls Facing Down
A6 B6 C6
A13 A12 A14
A5 B5 C5
A9 A8 A10
A4 B4 C4
WE RESET NC
A3 B3
RY/BY WP/ACC
C3
A18
A2 B2
A7 A17
C2
A6
A1 B1 C1
A3 A4 A2
D6
A15
D5
A11
D4
A19
D3
A20
D2
A5
D1
A1
E6
A16
E5
I/O7
E4
I/O5
E3
I/O2
E2
I/O0
E1
A0
F6
BYTE
G6 H6
I/O15(A-1) VSS
F5
I/O14
G5
I/O13
H5
I/O6
F4
I/O12
G4
VCC
H4
I/O4
F3
I/O10
G3
I/O11
H3
I/O3
F2
I/O 8
G2 H2
I/O9 I/O1
F1 G1 H1
CE OE VSS
PRELIMINARY (May, 2005, Version 0.0)
3
AMIC Technology, Corp.



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