A1240XL-xxxx Datasheet PDF - Actel

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A1240XL-xxxx
Actel

Part Number A1240XL-xxxx
Description FPGAs
Page 30 Pages


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v4.0.1
ACT2 Family FPGAs
Features
Up to 8000 Gate Array Gates
(20,000 PLD equivalent gates)
Replaces up to 200 TTL Packages
Replaces up to eighty 20-Pin PAL® Packages
Design Library with over 500 Macro Functions
Single-Module Sequential Functions
Wide-Input Combinatorial Functions
Up to 1232 Programmable Logic Modules
Up to 998 Flip-Flops
Datapath Performance at 105 MHz
16-Bit Accumulator Performance to 39 MHz
Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
Two High-Speed, Low-Skew Clock Networks
I/O Drive to 10 mA
Nonvolatile, User Programmable
Logic Fully Tested Prior to Shipment
1.0-micron CMOS Technology
Product Family Profile
Device
A1225A
A1240A
A1280A
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
2,500
6,250
63
25
4,000
10,000
100
40
8,000
20,000
200
80
Logic Modules
S-Modules
C-Modules
451 684 1,232
231 348 624
220 336 608
Flip-Flops (maximum)
382 568 998
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Channel
PLICE Antifuse Elements
36
15
250,000
36
15
400,000
36
15
750,000
User I/Os (maximum)
Packages1
Performance2
16-Bit Prescaled Counters
16-Bit Loadable Counters
16-Bit Accumulators
83
100 CPGA
100 PQFP
100 VQFP
84 PLCC
105 MHz
70 MHz
39 MHz
104
132 CPGA
144 PQFP
176 TQFP
84 PLCC
100 MHz
69 MHz
38 MHz
140
176 CPGA
160 PQFP
176 TQFP
84 PLCC
172 CQFP
85 MHz
67 MHz
36 MHz
Notes:
1. See the “Product Plan” on page 3 for package availability.
2. Performance is based on ‘–2’ speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1, Version 1.2,
dated 3-28-93, any analysis is not endorsed by PREP.
December 2000
© 2000 Actel Corporation
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ACT2 Family FPGAs
Description
The ACT2 family represents Actels second generation of
field programmable gate arrays (FPGAs). The ACT 2 family
presents a two-module architecture, consisting of C-modules
and S-modules. These modules are optimized for both
combinatorial and sequential designs. Based on Actels
patented channeled array architecture, the ACT 2 family
provides significant enhancements to gate density and
performance while maintaining downward compatibility
with the ACT 1 design environment and upward
compatibility with the ACT 3 design environment. The
devices are implemented in silicon gate, 1.0-µm, two-level
metal CMOS, and employ Actels PLICE® antifuse
technology. This revolutionary architecture offers gate array
design flexibility, high performance, and fast
time-to-production with user programming. The ACT 2
family is supported by the Designer and Designer Advantage
Systems, which offers automatic pin assignment, validation
of electrical and design rules, automatic placement and
routing, timing analysis, user programming, and diagnostic
probe capabilities. The systems are supported on the
following platforms: 386/486PC, Sun, and HP
workstations. The systems provide CAE interfaces to the
following design environments: Cadence, Viewlogic®,
Mentor Graphics®, and OrCAD.
Ordering Information
A1280 A – 1
PG 176
C
Application (Temperature Range)
C = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
Package Lead Count
Package Type
PL = Plastic J-Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
CQ = Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% faster than Standard
–2 = Approximately 25% faster than Standard
Die Revision
A = 1.0-µm CMOS process
Part Number
A1225 = 2500 Gates
A1240 = 4000 Gates
A1280 = 8000 Gates
2 v4.0



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Product Plan
Speed Grade*
Application
Std –1
2
CI
MB
A1225A Device
100-pin Ceramic Pin Grid Array (PG)
✔✔✔
100-pin Plastic Quad Flat Pack (PQ)
✔✔✔
100-pin Very Thin (1.0 mm) Quad Flat Pack (VQ) ✔ ✔ ✔
84-pin Plastic Leaded Chip Carrier (PL)
✔✔✔
A1240A Device
———
✔ ✔ ——
———
✔ ✔ ——
132-pin Ceramic Pin Grid Array (PG)
✔✔✔
176-pin Thin (1.4 mm) Quad Flat Pack (TQ)
144-pin Plastic Quad Flat Pack (PQ)
✔✔✔
84-pin Plastic Leaded Chip Carrier (PL)
✔✔✔
A1280A Device
✔ ✔
———
✔ ✔ ——
✔ ✔ ——
176-pin Ceramic Pin Grid Array (PG)
✔✔✔
176-pin Thin (1.4 mm) Quad Flat Pack (TQ)
160-pin Plastic Quad Flat Pack (PQ)
✔✔✔
172-pin Ceramic Quad Flat Pack (CQ)
✔✔✔
Contact your Actel sales representatives for product availability.
Applications: C = Commercial Availability: = Available *Speed Grade:
I = Industrial
P = Planned
M = Military
= Not Planned
B = MIL-STD-883
✔ ✔
———
✔ ✔ ——
✔ ✔
1 = Approx. 15% faster than Standard
2 = Approx. 25% faster than Standard
Device Resources
User I/Os
CPGA
PQFP
PLCC CQFP TQFP VQFP
Device Logic
Series Modules Gates 176-pin 132-pin 100-pin 160-pin 144-pin 100-pin 84-pin 172-pin 176-pin 100-pin
A1225A 451 2500 — — 83 — — 83
A1240A 684 4000 104
104
A1280A 1232 8000 140
125
72 — —
72 104
72 140 140
83
.
v4.0
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ACT2 Family FPGAs
Operating Conditions
Absolute Maximum Ratings1
Free air temperature range
Symbol
Parameter
Limits
Units
VCC DC Supply Voltage
VI Input Voltage
VO Output Voltage
IIO
I/O Source/Sink
Current2
0.5 to +7.0
0.5 to VCC +0.5
0.5 to VCC +0.5
±20
V
V
V
mA
TSTG Storage Temperature 65 to +150
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum
Ratingsmay cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Device should not be
operated outside the Recommended Operating Conditions.
2. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than VCC + 0.5 V or less than GND 0.5 V, the internal
protection diode will be forward biased and can draw excessive
current.
Recommended Operating Conditions
Commercia Industria
Parameter
l
l Military Units
Temperature
Range1
0 to +70
40 to
+85
55 to
+125
°C
Power
Supply
±5 ±10 ±10 %VCC
Tolerance
Note:
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
Electrical Specifications
Commercial
Industrial
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
VOH1
(IOH = 10 mA) 2
(IOH = 6 mA)
VOL1
(IOH = 4 mA)
(IOL = 10 mA) 2
(IOL = 6 mA)
VIL
VIH
Input Transition Time tR, tF2
CIO I/O Capacitance2, 3
Standby Current, ICC4 (typical = 1 mA)
Leakage Current5
2.4
3.84
3.7 3.7
0.5
0.33 0.40 0.40
0.3 0.8 0.3 0.8 0.3 0.8
2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3
500 500 500
10 10 10
2 10 20
10 10 10 10 10 10
Notes:
1. Only one output tested at a time. VCC = min.
2. Not tested, for information only.
3. Includes worst-case 176 CPGA package capacitance. VOUT = 0 V, f = 1 MHz.
4. All outputs unloaded. All inputs = VCC or GND, typical ICC = 1 mA. ICC limit includes IPP and ISV during normal operation.
5. VOUT , VIN = VCC or GND.
Units
V
V
V
V
V
V
V
ns
pF
mA
µA
4 v4.0



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