80C196KB Datasheet PDF - Intel Corporation

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80C196KB
Intel Corporation

Part Number 80C196KB
Description COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
Page 22 Pages


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8XC196KB 8XC196KB16
COMMERCIAL EXPRESS CHMOS MICROCONTROLLER
Y 8 Kbytes of On-Chip ROM OTP
Available
Y 232 Byte Register File
Y Register-to-Register Architecture
Y 28 Interrupt Sources 16 Vectors
Y 1 75 ms 16 x 16 Multiply (16 MHz)
Y 3 0 ms 32 16 Divide (16 MHz)
Y Powerdown and Idle Modes
Y Five 8-Bit I O Ports
Y 16-Bit Watchdog Timer
Y 12 MHz and 16 MHz Available
Y Dedicated 15-Bit Baud Rate Generator
Y Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y Full Duplex Serial Port
Y High Speed I O Subsystem
Y 16-Bit Timer
Y 16-Bit Up Down Counter with Capture
Y Pulse-Width-Modulated Output
Y Four 16-Bit Software Timers
Y 10-Bit A D Converter with Sample Hold
Y HOLD HLDA Bus Protocol
Y Extended Temperature Available
The 8XC196KB is a 16-bit microcontroller available in three different memory varieties ROMless (80C196KB)
8K ROM (83C196KB) and 8K OTP (One Time Programmable 87C196KB) The 8XC196KB is a high perform-
ance member of the MCS 96 microcontroller family The 8XC196KB has the same peripheral set as the
8096BH and has a true superset of the 8096BH instructions Intel’s CHMOS process provides a high perform-
ance processor along with low power consumption To further reduce power requirements the processor can
be placed into Idle or Powerdown Mode
Bit byte word and some 32-bit operations are available on the 80C196KB With a 16 MHz oscillator a 16-bit
addition takes 0 50 ms and the instruction times average 0 37 ms to 1 1 ms in typical applications
Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are
available for pulse or waveform generation The high-speed output can also generate four software timers or
start an A D conversion Events can be based on the timer or up down counter Also provided on-chip are an
A D converter serial port watchdog timer and a pulse-width-modulated output signal
The 8XC196KB has a maximum guaranteed frequency of 12 MHz The 8XC196KB16 has a maximum guaran-
teed frequency of 16 MHz All references to the 80C196KB also refer to the 80C196KB16 83C196KB Rxxx
87C196KB and 87C196KB16 unless otherwise noted The ROM device does not have a speed indicator at the
end of the device name Instead it has a ROM code number
With the commercial (standard) temperature option operational characteristics are guaranteed over the tem-
perature range of 0 C to a70 C With the extended temperature range option operational characteristics are
guaranteed over the temperature range of b40 C to a85 C
Package Designators N e 68-pin PLCC S e 80-pin QFP (commercial only) Prefix Designators T e Extend-
ed Temperature
Other brands and names are the property of their respective owners
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
July 1994
Order Number 270909-006



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Figure 1 8XC196KB Block Diagram
270909 – 1
2



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8XC196KB 8XC196KB16
PROCESS INFORMATION
This device is manufactured on P629 0 and 629 1 a
CHMOS III-E process Additional process and reli-
ability information is available in Intel’s Components
Quality and Reliability Handbook Order Number
210997
270909 – 2
EXAMPLE N87C196KB16 is 68-Lead PLCC
OTPROM 16 MHz
For complete package dimensional data refer to the
Intel Packaging Handbook (Order Number 240800)
NOTE
1 EPROMs are available as One Time Programmable
(OTPROM) only
Figure 2 The 8XC196KB Nomenclature
Table 1 Thermal Characteristics
Package
Type
ija
ijc
PLCC
35 C W
13 C W
QFP
70 C W
4C W
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation Values will change
depending on operation conditions and application See
the Intel Packaging Handbook (order number 240800) for a
description of Intel’s thermal impedance test methodology
Table 2 8XC196KB Memory Map
Description
Address
External Memory or I O
0FFFFH
04000H
Internal ROM EPROM or External
Memory (Determined by EA)
3FFFH
2080H
Reserved Must contain FFH
(Note 5)
207FH
2040H
Upper Interrupt Vectors
203FH
2030H
ROM EPROM Security Key
202FH
2020H
Reserved Must contain FFH
(Note 5)
201FH
201AH
Reserved Must Contain 20H
(Note 5)
2019H
CCB
2018H
Reserved Must contain FFH
(Note 5)
2017H
2014H
Lower Interrupt Vectors
2013H
2000H
Port 3 and Port 4
1FFFH
1FFEH
External Memory
1FFDH
0100H
232 Bytes Register RAM (Note 1)
00FFH
0018H
CPU SFR’s (Notes 1 3)
0017H
0000H
NOTES
1 Code executed in locations 0000H to 00FFH will be
forced external
2 Reserved memory locations must contain 0FFH unless
noted
3 Reserved SFR bit locations must contain 0
4 Refer to 8XC196KB quick reference for SFR descrip-
tions
5 WARNING Reserved memory locations must not be
written or read The contents and or function of these lo-
cations may change with future revisions of the device
Therefore a program that relies on one or more of these
locations may not function properly
3



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270909 – 3
Figure 3 68-Pin Package (PLCC Top View)
NOTE
The above pin out diagram applies to the OTP (87C196KB) device The OTP device uses all of the programming pins shown
above The ROM (83C196KB) device only uses programming pins AINC PALE PMODE n and PROG The ROMless
(80C196KB) doesn’t use any of the programming pins
4



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