74LVC543 Datasheet PDF - Philips

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74LVC543
Philips

Part Number 74LVC543
Description Octal D-type registered transceiver
Page 9 Pages

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Philips Semiconductors
Octal D-type registered transceiver; 3-state
Product Specification
74LVC543
FEATURES
• Wide supply voltage range of
1.2 V to 3.6 V
• In accordance with JEDEC
standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Combines 74LVC245 and
74LVC373 type functions in
one chip
• 8-bit octal transceiver with
D-type latch
• Back-to-back registers for
storage
• Seperate controls for data flow
in each direction
• 3-state non-inverting outputs
for bus oriented applications
DESCRIPTION
The 74LVC543 is a
high-performance, low-power,
low-voltage, Si-gate CMOS device
and superior to most advanced
CMOS compatible TTL families.
The 74LVC543 is an octal registered
transceiver containing two sets of
D-type latches for temporary storage
of the data flow in either direction.
Seperate latch enable (LEAB, LEBA)
and output enable (OEAB, OEBA)
inputs are provided for each register
to permit independent control of
inputting and outputting in either
direction of the data flow.
The ’543 contains eight D-type
latches, with seperate inputs and
controls for each set. For data flow
from A to B, for example, the A-to-B
enable (EAB) input must be LOW in
order to enter data from A0-A7 or
take data from B0-B7, as indicated in
the function table. With EAB LOW, a
LOW signal on the A-to-B latch
enable (LEAB) input makes the
A-to-B latches transparent; a
subsequent LOW-to HIGH transition
of the LEAB signal puts the A data
into the latches where it is stored
and the B outputs no longer change
with the A inputs. With EAB and OEAB
both low, the 3-state B output
buffers are active and display the
data present at the outputs of the A
latches
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS TYPICAL UNIT
tPHL/tPLH
CI
CI/O
CPD
propagation delay
An to Bn
input capacitance
CL = 50 pF
VCC = 3.3 V
input/output capacitance
power dissipation
capacitance per latch
notes 1 and 2
5.4
5.0
10
33
ns
pF
pF
pF
Notes to the quick reference data
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD x VCC2 x fi + Σ (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL x VCC2 x fo) = sum of outputs.
2. The condition is VI = GND to VCC.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
PINS PACKAGE MATERIAL
CODE
74LVC543D 24
SO
plastic
SO20/SOT137
74LVC543DB 24 SSOP
plastic SSOP20/SOT340
74LVC543PW 24 TSSOP
plastic SSOP20/SOT355
PINNING
PIN SYMBOL
NAME AND FUNCTION
1
2
3, 4, 5, 6, 7,
8, 9, 10
LEBA
OEBA
A0 to A7
’B’ to ’A’ latch enable input (active LOW)
’B’ to ’A’ output enable input (active LOW)
’A’ data inputs/outputs
11 EAB ’B’ to ’A’ enable input (active LOW)
12
GND
ground (0 V)
22, 21, 20, 19,
18, 17, 16, 15
B0 to B7
’B’ data inputs/outputs
13
OEAB
’A’ to ’B’ output enable input (active LOW)
14
LEAB
’A’ to ’B’ latch enable input (active LOW)
23 EBA ’A’ to ’B’ enable input (active LOW)
24 VCC positive supply voltage
March 1993
1

74LVC543 datasheet pdf
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