74LVC543 Datasheet PDF - Philips

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74LVC543
Philips

Part Number 74LVC543
Description Octal D-type registered transceiver
Page 9 Pages


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Philips Semiconductors
Octal D-type registered transceiver; 3-state
Product Specification
74LVC543
FEATURES
• Wide supply voltage range of
1.2 V to 3.6 V
• In accordance with JEDEC
standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Combines 74LVC245 and
74LVC373 type functions in
one chip
• 8-bit octal transceiver with
D-type latch
• Back-to-back registers for
storage
• Seperate controls for data flow
in each direction
• 3-state non-inverting outputs
for bus oriented applications
DESCRIPTION
The 74LVC543 is a
high-performance, low-power,
low-voltage, Si-gate CMOS device
and superior to most advanced
CMOS compatible TTL families.
The 74LVC543 is an octal registered
transceiver containing two sets of
D-type latches for temporary storage
of the data flow in either direction.
Seperate latch enable (LEAB, LEBA)
and output enable (OEAB, OEBA)
inputs are provided for each register
to permit independent control of
inputting and outputting in either
direction of the data flow.
The ’543 contains eight D-type
latches, with seperate inputs and
controls for each set. For data flow
from A to B, for example, the A-to-B
enable (EAB) input must be LOW in
order to enter data from A0-A7 or
take data from B0-B7, as indicated in
the function table. With EAB LOW, a
LOW signal on the A-to-B latch
enable (LEAB) input makes the
A-to-B latches transparent; a
subsequent LOW-to HIGH transition
of the LEAB signal puts the A data
into the latches where it is stored
and the B outputs no longer change
with the A inputs. With EAB and OEAB
both low, the 3-state B output
buffers are active and display the
data present at the outputs of the A
latches
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS TYPICAL UNIT
tPHL/tPLH
CI
CI/O
CPD
propagation delay
An to Bn
input capacitance
CL = 50 pF
VCC = 3.3 V
input/output capacitance
power dissipation
capacitance per latch
notes 1 and 2
5.4
5.0
10
33
ns
pF
pF
pF
Notes to the quick reference data
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD x VCC2 x fi + Σ (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL x VCC2 x fo) = sum of outputs.
2. The condition is VI = GND to VCC.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
PINS PACKAGE MATERIAL
CODE
74LVC543D 24
SO
plastic
SO20/SOT137
74LVC543DB 24 SSOP
plastic SSOP20/SOT340
74LVC543PW 24 TSSOP
plastic SSOP20/SOT355
PINNING
PIN SYMBOL
NAME AND FUNCTION
1
2
3, 4, 5, 6, 7,
8, 9, 10
LEBA
OEBA
A0 to A7
’B’ to ’A’ latch enable input (active LOW)
’B’ to ’A’ output enable input (active LOW)
’A’ data inputs/outputs
11 EAB ’B’ to ’A’ enable input (active LOW)
12
GND
ground (0 V)
22, 21, 20, 19,
18, 17, 16, 15
B0 to B7
’B’ data inputs/outputs
13
OEAB
’A’ to ’B’ output enable input (active LOW)
14
LEAB
’A’ to ’B’ latch enable input (active LOW)
23 EBA ’A’ to ’B’ enable input (active LOW)
24 VCC positive supply voltage
March 1993
1



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Philips Semiconductors
Octal registered transceiver; 3-state
LEBA 1
OEBA 2
A0 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
EAB 11
GND 12
543
24 VCC
23 EBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
Fig.1 Pin configuration.
2 1EN3
23 G1
1 1C5
13 2EN4
11 G2
14 2C6
3 22
3 5D
6D 4
4
21
5 20
6 19
7 18
8 17
9 16
10 15
Fig3. IEC logic symbol.
Objective Specification
74LVC543
3 A0
4 A1
5 A2
6 A3
7 A4
8 A5
9 A6
10 A7
2 OEBA
13 OEAB
11 EAB
23 EBA
14 LEAB
1 LEBA
B0 22
B1 21
B2 20
B3 19
B4 18
B5 17
B6 16
B7 15
Fig.2 Logic symbol.
March 1993
2



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Philips Semiconductors
Octal registered transceiver; 3-state
Objective Specification
74LVC543
OEBA
EBA
LEBA
OEAB
EAB
LEAB
An
8 identical
channels
LE
D
LE
D
Bn
to 7 other channels
Fig.4 Logic diagram
FUNCTION TABLE
OEXX
H
X
L
L
L
L
L
L
L
INPUTS
EXX LEXX
XX
HX
L
L
L
L
LL
LL
LH
DATA
X
X
h
l
h
l
H
L
X
OUTPUTS
Z
Z
Z
Z
H
L
H
L
NC
STATUS
Disabled
Disabled
Disabled + Latch
Latch + Display
Transparent
Hold
XX = AB for A-to-B direction, BA for B-to-A direction
H = HIGH voltage level
L = LOW voltage level
h = High state must be present one setup time before the LOW-TO-HIGH transition of LEAB, LEBA, EAB, EBA
l = Low state must be present one setup time before the LOW-TO-HIGH transition of LEAB, LEBA, EAB, EBA
X = Don’t care
= LOW-to-HIGH level transition
NC = No change
Z = High impedance OFF state
March 1993
3



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Philips Semiconductors
Octal registered transceiver; 3-state
Objective Specification
74LVC543
FAMILY DESCRIPTION
The LVC family comprises very fast
low-power logic ICs fabricated in a
sub-micron CMOS process.
LVC ICs with 3.3 V ±0.3 V supply
operate at the same speed as FAST
bipolar logic and consumes only
a fraction of the power. The LVC
family functions with supply
voltages down to 2.7 V. The
reduction from the conventional
5.0 V to 3.3 V reduces the output
swing leading to a much lower
dynamic power dissipation. Pin and
function compatibility with FAST
ensures an easy transfer of
existing systems into new 3.3 V
systems.
RECOMMENDED OPERATING CONDITIONS FOR THE LVC FAMILY
SYMBOL
PARAMETER
MIN. MAX.
VCC
DC supply voltage (for max. speed
performance)
2.7 3.6
VCC
DC supply voltage (for low-voltage
applications)
1.2 3.6
VI DC input voltage range
VI/O DC input voltage range for I/Os
VO DC output voltage range
0 5.5
0 VCC
0 VCC
Tamb
operating ambient temperature range in
free air
−40
+85
tr, tf input rise and fall times
0 20
0 10
UNIT
V
CONDITIONS
V
V
V
V
°C
ns/V
see DC and AC
characteristics per
device
VCC = 1.2 to 2.7 V
VCC = 2.7 to 3.6 V
LIMITING VALUES FOR THE LVC FAMILY (Note 1)
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
PARAMETER
MIN. MAX. UNIT
CONDITIONS
VCC
IIK
VI
VI/O
IOK
VO
IO
IGND, ICC
Tstg
Ptot
DC supply voltage
−0.5 +4.6 V
DC input diode current
DC input voltage
− −50
−0.5 +5.5
mA VI < 0
V note 2
DC input voltage range for I/Os −0.5 VCC + 0.5 V
DC output diode current
±50 mA VO > VCC or VO < 0
DC output voltage
−0.5 VCC + 0.5 V note 2
DC output source or sink current −
±50 mA VO = 0 to VCC
DC VCC or GND current
±100 mA
storage temperature range
−60 +150 °C
power dissipation per package
- plastic mini-pack (SO)
− 500 mW above + 70°C derate linearly with 8 mW/K
- plastic shrink mini-pack
− 500 mW above + 60°C derate linearly with 5.5 mW/K
(SSOP and TSSOP)
Notes to the limiting values
1. Stresses beyond those listed
those under ’recommended
may cause permanent damage to operating conditions’ is not implied.
the device. These are stress
Exposure to absolute maximum
ratings only and functional
rated conditions for extended
operation of the device at these periods may affect device reliability.
or any other conditions beyond
2. The input and output voltage
ratings may be exceeded if the
input and output current ratings
are observed.
March 1993
4



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